PCI Target

4-1–4-45

Abort 2-1, 10-5

accesses 10-19, 10-20

8- or 16-bit Local Bus, to 2-2

Big Endian/Little Endian mode, Local Bus 2-10 partial Lword 2-10

Big Endian/Little Endian cycle reference table 2-11 BTERM# input 2-9

bursting 1-3

command codes 2-1

Delayed Read mode 1-5, 4-2, 10-34

Delayed Write mode 1-3, 1-5, 10-34

timing diagram 5-4

description 1-1

FIFO depth 1-3, 1-5

interface chip 1-3

power management 7-1 Power mode example 7-3

Read Ahead mode 1-1, 1-3, 2-10, 3-1, 10-35

READY# Timeout, Local Bus 1-5, 10-34

response (CNTRL) 10-3, 10-34–10-35

SMARTarget 1-1

timing diagram 4-16

transactions 1-3

wait states 2-8

PCIBAR0 3-7, 4-4, 10-7

PCIBAR1 3-7, 4-4, 10-7

PCIBAR2 4-4, 10-8

PCIBAR3 4-4, 10-8

PCIBAR4 4-4, 10-9

PCIBAR5 4-4, 10-9

PCIBISTR (not supported) 10-6

PCICCR 3-3, 10-5

PCICIS (not supported) 10-10

PCICLSR 3-6, 10-6

PCICR 6-2, 10-4

PCIERBAR 3-7, 4-4, 10-10

PCIHTR 3-6, 10-6

PCIIDR 3-3, 10-4

PCIILR 3-3, 10-11

PCIIPR 3-3, 10-11

PCILTR (not supported) 10-6 PCIMGR (not supported) 10-11 PCIMLR (not supported) 10-11 PCIREV 3-3, 10-5

PCISID 3-3, 10-10

PCISR 3-3, 7-1, 10-5

PCISVID 3-3, 10-4, 10-10

PCLK 11-8, 12-2, 13-3, 13-6

performance features 1-3

PERR# 11-8, 13-3, 13-6

PCI Target

to pins, no connect (NC, µBGA)

physical specs 13-1–13-8

PICMG 2.1, R2.0 1-2, 1-3, 8-1, 8-1

Pinout

µBGA 13-6

PQFP 13-3

Pins

BD_SEL# 8-1

CPCISW 8-1

ENUM# 1-2, 8-1

LEDon# 8-1

VIO8-1

Дата добавления: 2015-07-10