Address

address-to-data 2-8

boundary 2-9

burst start 2-10

bus state 2-3

chip select base registers 10-31, 10-32

cycle 2-9, 2-10

decode 10-10, 10-18

EROMBA 10-20

invariance 2-1, 2-11

local address space bus region descriptor registers 10-21–10-27

local address space local base address registers 10-19– 10-20

local address space range registers 10-16–10-17 local bits 2-2

mapping 4-3, 4-4

Multiplexed and Non-Multiplexed Bus modes 11-1 Multiplexed Bus mode 11-12

Non-Multiplexed Bus mode 11-15 PCI 3-7, 4-3–4-7, 10-15

base address registers 10-7–10-9 system bus interface pins 11-7

pointer 10-1

PROT_AREA 10-33

Read Ahead mode, PCI Target 4-3

register mapping 10-2–10-3

registers 1-5, 3-3, 4-1

spaces 1-1, 1-3, 1-5, 2-10, 5-1–5-2

stepping 10-4

VPD 9-1

Address/Data 1-3, 2-3, 2-4, 2-6, 2-9, 4-4, 10-4, 11-13

ADS# 11-12, 11-15, 13-3, 13-6

ALE 2-4, 11-12, 11-15, 13-3, 13-6

arbitration, Local Bus 2-3, 2-5

timing diagram 2-6, 4-9

Architecture

boundary scan 11-18 RISC and bridge 2-2

Asynchronous

resets 1-2, 8-1

Atomic operations

LLOCKo# 2-4, 11-3, 11-9, 13-3, 13-6

LOCK# 11-7, 13-3, 13-6

locked 4-1

B

B0-B3power management states 7-1

Back-to-back

fast 10-4, 10-5

timing diagrams 4-23–4-26

BCLKo 11-9, 13-3, 13-6

BD_SEL# 8-1, 11-1, 11-6, 13-3, 13-6

Big Endian

See Endian, Big/Little

BIOS 2-1, 3-6, 6-1, 7-1, 10-18

BLAST# 11-12, 11-15, 13-3, 13-6

board routing, µBGA 13-7–13-8

bridge architecture 2-2

BTERM# 2-8, 2-9, 11-1, 11-12, 11-15, 13-3, 13-6

Buffers

ENUM# three-state 11-2

I/O 1-2, 8-1, 8-2, 11-4

output 8-1, 11-5

Posted Memory Write (PMW), bridge 2-2

Bursts

continuous mode 2-9–2-10 expansion ROM enable 10-29 last and terminate 11-12, 11-15

memory space enable 10-21–10-27 PCI 4-1, 4-3, 4-4

period device 10-11 read and write 11-7

timing diagrams 4-16–4-20, 4-29–4-31, 4-36–4-41

transfers 1-1, 1-3

bus modes

to deadlock, avoided with PMW

Дата добавления: 2015-07-10