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Pull-Up and Pull-Down Resistor Recomme Pin Description

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    ndations
I/O Pins (Pin Type I/O)

This section discusses the pull-up and pull-down resistor requirements for the following Local Bus I/O pins—GPIO0/WAITo#, GPIO1/LLOCKo#, GPIO2/ CS2#, GPIO3/CS3#, GPIO4/LA27, GPIO5/LA26, GPIO6/LA25, GPIO7/LA24, GPIO8, LAD/LD[31:0].

The PCI 9030 drives Local Bus I/O signals when it owns the Local Bus, and floats Local Bus I/O signals when it does not own the Local Bus (LGNT asserted). During PCI reset, the PCI 9030 drives the GPIO4/ LA27, GPIO5/LA26, GPIO6/LA25, GPIO7/LA24, and

LAD/LD[31:0] signals low. (Refer to Table 11-4 for resistor requirements and PCI 9030 Errata #4.)


 

Signal Requirements
GPIO0/WAITo# If GPIO[8:0] are configured as inputs and not used, pull or tie these pins to VDDor VSS. Under default register configuration, the following pins are configured as inputs—GPIO0/WAITo#, GPIO1/ LLOCKo#, GPIO2/CS2#, GPIO3/CS3#, and GPIO8. Note: Refer to PCI 9030 Errata #2, regarding the GPIO[8:0] pins which, when configured as outputs, are floated when the PCI 9030 does not own the Local Bus.
GPIO1/LLOCKo#
GPIO2/CS2#
GPIO3/CS3#
GPIO4/LA27
GPIO5/LA26
GPIO6/LA25
GPIO7/LA24
GPIO8
    LAD/LD[31:0] Connect unused Data Bus pins to a pull-up or pull-down resistor. Depending upon design, it is recommended to add resistors to all Data pins. When reading from a local device, the LAD/LD lines are effectively floated, and if the local device is not driving these pins (such as during wait states), then noise can couple into the LAD/LD inputs.

 

Table 11-4. I/O Pin Pull-Up and Pull-Down Resistor Requirements


 

PINOUT COMMON TO ALL BUS MODES

 

Table 11-5. Power and Ground Pins (176-Pin PQFP)

 

  Symbol   Signal Name Total Pins Pin Type PQFP Pin Number   Function
  VDD     Power (+3.3V)     I 1, 14, 32, 45, 56, 70, 85, 100, 117, 133, 162 3.3V power supply pins for core and I/O buffers. Liberal 0.01 to 0.1 µF decoupling capacitors should be placed near the PCI 9030.
  VI/O Voltage Input/Output     I     System voltage select, 3.3 or 5V, from the PCI Bus.
  VSS     Ground         I 13, 31, 44, 57, 66, 78, 88, 101, 113, 122, 132, 146, 163, 176     Ground pins.
Total          

 

Note: The die contains 224 pads. Power and Grounds are double bounded in the PQFP packages to meet proper drive strength of the buffers.

 

 

Table 11-6. Power, Ground, and No Connect Pins (180-Pin µBGA)

 

    Symbol     Signal Name Total Die Pads   Total Pins   Pin Type   µBGA Pin Number     Function
NC Spare   A1, A14, P1, P14 Applicable only to 180-Pin µBGA. Unused.
  VDD   Power (+3.3V)       I B2, B6, B13, E1, F11, J5, K13, M8, N2, N5, P12 3.3V power supply pins for core and I/O buffers. Liberal 0.01 to 0.1 µF decoupling capacitors should be placed near the PCI 9030.
VI/O Voltage Input/Output     I L5   System voltage select, 3.3 or 5V, from the PCI Bus.
  VSS   Ground       I A2, A10, B14, C6, E13, F5, G13, J3, J10, K6, L7, N1, N10, P13   Ground pins.
Total            

 

 

Table 11-7. Serial EEPROM Interface Pins

 

  Symbol   Signal Name Total Pins Pin Type PQFP Pin Number µBGA Pin Number   Function
  EECS Serial EEPROM Chip Select   O TP 6 mA     C7   Serial EEPROM chip select.
  EEDI Serial EEPROM Data In   O TP 6 mA     D6   Write data to serial EEPROM.
    EEDO   Serial EEPROM Data Out         I         E7 Read data from serial EEPROM. When the BD_SEL#/TEST input pin is pulled high for Test mode, the EEDO input functions as an IDDQ Test Enable pin. When BD_SEL#/TEST input is high and EEDO is input low, the PCI 9030 output buffers are in a quiescent state and the PCI 9030 draws minimum power. When BD_SEL#/TEST and EEDO inputs are both high, all outputs except LEDon# are floated. However, the analog precharge circuits are active, and power consumption is consequently higher than a quiescent state, but is less than that consumed during normal operation.
  EESK   Serial Data Clock   O TP 6 mA     A7   Serial EEPROM clock pin.
Total            

 

Note: The serial EEPROM interface operates at core voltage (+3.3V). The PCI 9030 requires a serial EEPROM that can operate at 250 kHz, and supports sequential reads.


 

 


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Читайте в этой же книге: Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1 | Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer | Register 10-27. (PMC; PCI:42h) Power Management Capabilities | Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status | Register 10-39. (LAS1RR; 04h) Local Address Space 1 Range | Register 10-42. (EROMRR; 10h) Expansion ROM Range | Register 10-56. (CS3BASE; 48h) Chip Select 3 Base Address | Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control | Register 10-60. (GPIOC; 54h) General Purpose I/O Control | Register 10-61. (PMDATASEL; 70h) Hidden 1 Power Management Data Select |
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Table 11-2. Input Pin Pull-Up and Pull-Down Resistor Requirements| Table 11-8. Test and Debug Pins

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