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Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer

Читайте также:
  1. CONTEXT AND REGISTER
  2. Figure 3-2. PCI 9030 Internal Register Access
  3. Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1
  4. Register 10-2. (PCICR; PCI:04h) PCI Command
  5. Register 10-27. (PMC; PCI:42h) Power Management Capabilities
  6. Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status

 

Bit Description Read Write Value after Reset
  7:0 New Capability Pointer.Provides an offset into PCI Configuration Space for location of the first item in the New Capabilities Linked List. Bits [1:0] are reserved by PCI r2.2, and should be set to 00 (the byte value points to an Lword boundary.) Note: These bits must always contain the default value 40h. (Refer to PCI 9030 Errata #9.)   Yes     Serial EEPROM   40h
31:8 Reserved. Yes No 0h


 

 

Register 10-21. (PCIILR; PCI:3Ch) PCI Interrupt Line

 

Bit Description Read Write Value after Reset
    7:0 Interrupt Line Routing Value.Indicates to which system interrupt controller(s) input the interrupt line is connected. The PCI 9030 does not use this value, rather the value is used by device drivers and operating systems for priority and vector information. Values in this register are system-architecture specific. For x86-based PCs, the values in this register correspond to IRQ numbers (0 through 15) of the standard dual 8259 interrupt controller configuration. The value 255 is defined as “unknown” or “no connection” to the interrupt controller. Values 15 through 255 are reserved.     Yes     Yes     0h

 

Дата добавления: 2015-07-10; просмотров: 139 | Нарушение авторских прав

Читайте в этой же книге: Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only | Chip Select Timing Diagrams Local Chip Selects | Figure 6-1. Interrupt and Error Sources | Timing Diagram 6-3. GPIO[8:0] as Outputs | System Changes Power Mode Example PCI Power Management | Controlling Connection Processes CompactPCI Hot Swap | Figure 9-1. VPD Capabilities | Table 10-2. PCI Configuration Register Address Mapping | Register 10-2. (PCICR; PCI:04h) PCI Command | Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type |
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Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1| Register 10-27. (PMC; PCI:42h) Power Management Capabilities
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