Register 10-59. (cntrl; 50h) PCI Target Response, serial eeprom, and Initialization Control

Bit	Description	Read	Write	Value after Reset
5:0	Reserved.	Yes	No	0h
	PCI Target Write FIFO Full Condition.Value of 1 guarantees that when the PCI Target Write FIFO is full with PCI Target Write data, there is always one location remaining empty for the PCI Target Read address to be accepted by the PCI 9030. Value of 0 Retries all PCI Target Read accesses when the PCI Target Write FIFO is full with PCI Target Write data.	Yes	Yes
	Local Arbiter LGNT Signal Select Enable.Value of 1 selects LGNT to remain active until LREQ is de-asserted, although the PCI 9030 has a PCI Target transaction pending. Value of 0 selects LGNT to be de-asserted as soon as the PCI 9030 detects a PCI Target transaction pending and waits for LREQ to be de-asserted (Preempt condition).	Yes	Yes
	READY# Timeout Enable.Value of 1 enables READY# timeout enable.	Yes	Yes
	READY# Timeout Select.Values: 1 = 64 clocks 0 = 32 clocks	Yes	Yes
11:10	PCI Target Delayed Write Mode.Delay in LCLKs of ADS# from valid address. Values: 00 = 0 LCLKs 10 = 8 LCLKs 01 = 4 LCLKs 11 = 16 LCLKs	Yes	Yes
13:12	PCI Configuration Base Address Register (PCIBAR) Enables.Values: 00, 11 = PCIBAR0 (Memory) and PCIBAR1 (I/O) enabled 01 = PCIBAR0 (Memory) only 10 = PCIBAR1 (I/O) only Note: PCIBAR0 and PCIBAR1 should be enabled for the PC platform.	Yes	Yes
	PCI r2.2 Features Enable.When set to 1, the PCI 9030 performs all PCI Read and Write transactions in compliance with PCI r2.2. Setting this bit enables Delayed Reads, 215PCI Clock timeout on Retries, 16- and 8-clock PCI latency rules, and enables the option to select PCI Read No Write Mode (Retries for writes) (bit [17]) and/or PCI Read with Write Flush Mode (bit [15]). Refer to Section 4.2.1.2 for additional information. Value of 0 causes TRDY# to remain de-asserted on reads until Read data is available. If Read data is not available before the PCI Target Retry Delay Clocks counter (bits [22:19]) expires, a PCI Retry is issued.	Yes	Yes
	PCI Read with Write Flush Mode.When the PCI r2.2 Features Enable bit is set (bit [14]=1), value of 1 flushes a pending Delayed Read cycle if a Write cycle is detected. Value of 0 (or bit [14]=0) does not affect a pending Delayed Read when a Write cycle occurs.	Yes	Yes

Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control (Continued)

Bit	Description	Read	Write	Value after Reset
	PCI Read No Flush Mode.Value of 1 does not flush the Read FIFO if the PCI Read cycle completes (PCI Target Read Ahead mode). Value of 0 flushes the Read FIFO if a PCI Read cycle completes. Read Ahead mode requires that Prefetch be enabled in the LAS x BRD and/or EROMBRD registers for the Memory-Mapped spaces that use Read Ahead mode. The PCI 9030 flushes its Read FIFO for each I/O-Mapped access.	Yes	Yes
	PCI Read No Write Mode (PCI Retries for Writes).When the PCI r2.2 Features Enable bit is set (bit [14]=1), value of 1 forces a PCI Retry on writes if a Delayed Read is pending. Value of 0 (or bit [14] =0) allows writes to occur while a Delayed Read is pending.	Yes	Yes
	PCI Write Release Bus Mode Enable.Value of 1 disconnects if the Write FIFO becomes full. Value of 0 de-asserts TRDY# until space is available in the Write FIFO (PCI Write Hold Bus mode).	Yes	Yes
22:19	PCI Target Retry Delay Clocks.Number of PCI clocks (multiplied by 8) from the beginning of a PCI Target access, after which a PCI Retry is issued if the transfer has not completed. Valid for Read cycles only if bit [14]=0. Valid for Write cycles only if bit [18]=0.	Yes	Yes	Fh
	PCI Target LOCK# Enable.Value of 1 enables PCI Target locked sequences. Value of 0 disables PCI Target locked sequences.	Yes	Yes
	Serial EEPROM Clock for PCI Bus Reads or Writes to Serial EEPROM.Toggling this bit generates a serial EEPROM clock. (Refer to manufacturer’s data sheet for the particular serial EEPROM being used.)	Yes	Yes
	Serial EEPROM Chip Select.For PCI Bus reads or writes to the serial EEPROM, setting this bit to 1 provides serial EEPROM chip select.	Yes	Yes
	Write Bit to Serial EEPROM.For writes, this output bit is the input to serial EEPROM. Clocked into the serial EEPROM by serial EEPROM clock.	Yes	Yes
	Read Serial EEPROM Data Bit.For reads, this input bit is the output of serial EEPROM. Clocked out of the serial EEPROM by serial EEPROM clock.	Yes	No	—
	Serial EEPROM Present.Value of 1 indicates a blank or programmed serial EEPROM is present.	Yes	No
	Reload Configuration Registers.When set to 0, writing 1 causes the PCI 9030 to reload the Local Configuration registers from serial EEPROM.	Yes	Yes
	PCI Adapter Software Reset.Value of 1 resets the PCI 9030 and issues a reset to the Local Bus (LRESETo# asserted). The PCI 9030 remains in this reset condition until the PCI Host clears this bit. The contents of the PCI and Local Configuration registers are not reset. The PCI Interface is not reset. Note: If PCI Target Read Ahead mode is enabled (bit [16]=1), disable it prior to a software reset, or if following a software reset, perform a PCI Target read of any valid Local Bus address, except the next sequential Lword referenced from the last PCI Target read, to flush the PCI Target Read FIFO.	Yes	Yes
	Disconnect with Flush Read FIFO.When the PCI r2.2 Features Enable bit is set (bit [14]=1), value of 1 causes acceptance of a new Read request with flushing of the Read FIFO when a PCI Target Read request does not match an existing, pending Delayed Read in the Read FIFO. Value of 0, or clearing of the PCI r2.2 Features Enable bit (bit [14]=0), causes a new Target Read request (different command, address and/or byte enables) to be Retried when a Delayed Read is pending in the Read FIFO.	Yes	Yes

Дата добавления: 2015-07-10