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Figure 4-2. PCI Target Read Ahead Mode

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  5. Figure 3-2. PCI 9030 Internal Register Access
  6. Figure 4-1. PCI Target Delayed Read Mode

Note: The figure represents a sequence of Bus cycles.

 

PCI Target Delayed Write Mode

The PCI 9030 supports PCI Target Delayed Write mode transactions, where posted Write data accumulates in the PCI Target Write FIFO before the PCI 9030 requests a Write transaction (ADS# and/or ALE assertion) to be performed on the Local Bus. PCI Target Delayed Write mode is programmable to delay the ADS# and ALE assertion for the amount of Local clocks selected in CNTRL[11:10]. This feature is useful for gaining higher throughput during PCI Target Write Burst transactions for conditions in which the PCI clock frequency is slower than the Local clock frequency.

 

PCI Target Local Bus

READY# Timeout Mode

The PCI 9030 supports PCI Target Local Bus READY# Timeout mode transactions, where the PCI 9030 asserts an internal READY# signal to recover from stalling the Local and PCI Buses. The PCI Target Local Bus READY# Timeout mode transaction is programmable to select the amount of Local clocks before READY# times out (CNTRL[9:8]). If a Local Target stalls with a READY# assertion


 


during PCI Target Write transactions, the PCI 9030 empties the Write FIFO by dumping the data into the Local Bus and does not pass an error condition to the PCI Bus Initiator. During PCI Target Read transactions, the PCI 9030 issues a PCI Target Abort to the PCI Bus Initiator every time the PCI Target

Local Bus READY# Timeout is detected.


The PCI 9030 supports on-the-fly Endian conversion for Spaces 0, 1, 2, and 3, and Expansion ROM. The Local Bus can be Big/Little Endian by using the programmable internal register configuration.

Note: The PCI Bus is always Little Endian.


 

PCI Target Transfer

A PCI Bus Master addressing the Memory space decoded for the Local Bus initiates transactions. Upon a PCI Read/Write, the PCI 9030 being a Local Bus Master executes a transfer, at which time it reads data into the PCI Target Read FIFO or writes data to the Local Bus.

For a PCI Direct access to the Local Bus, the

PCI 9030 has a 32-Lword (128-byte) Write FIFO and an 16-Lword (64-byte) Read FIFO. The FIFOs


Master


 

FRAME#, C/BE#,

AD (addr) IRDY#, AD (data) DEVSEL#, TRDY#


Slave Master


 

 

    PCI 9030
LA, ADS#, LW/R#

 

LAD, BLAST# LRDYi#


Slave


enable the Local Bus to operate independently of the PCI Bus.


Дата добавления: 2015-07-10; просмотров: 153 | Нарушение авторских прав

Читайте в этой же книге: Table 2-3. READY# Data Transfers | Table 2-4. MODE Pin-to-Bus Mode Cross-Reference | Table 2-6. Burst and Bterm on the Local Bus | Table 2-8. PCI Target Single and Burst Reads | Table 2-9. Byte Number and Lane Cross-Reference | Little Endian | Table 2-14. Lower Byte Lane Transfer— 8-Bit Local Bus | Table 3-2. Serial EEPROM Register Load Sequence | Figure 3-2. PCI 9030 Internal Register Access | Timing Diagram 3-5. PCI Memory Read from Local Configuration Register |
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Figure 4-1. PCI Target Delayed Read Mode| Figure 4-3. PCI Target Write
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