Figure 4-3. PCI Target Write

For Write transfers, if the Write FIFO becomes full, the PCI 9030 is programmable to disconnect, or retain the PCI Bus while generating wait states (TRDY# de-asserted) (CNTRL[18]).

For PCI Read transactions from the Local Bus, the PCI 9030 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9030 prefetches up to 16 Lwords (in Continuous Prefetch mode) from the

Master

FRAME#, C/BE#,

AD (addr) IRDY# DEVSEL#

Slave Master

LA, ADS#, LW/R#, BLAST#

LRDYi#, LAD

Slave

Local Bus. Unused Read data is flushed from the FIFO. For Read accesses mapped to PCI I/O space, the PCI 9030 does not prefetch Read data. Rather, it breaks each read of a Burst cycle into a single Address/Data cycle on the Local Bus.

The PCI Target Retry Delay Clocks bits (CNTRL[22:19]) can be used to program the period of time in which the PCI 9030 holds off TRDY#. The PCI 9030 issues a Retry to the PCI Bus Transaction Master when the programmed time period expires. This occurs when the PCI 9030 cannot gain Local Bus control and return TRDY# within the programmed time period or the Local Bus is slowly emptying the Write FIFO, and filling the Read FIFO.

TRDY#, AD (data)

    PCI 9030

Figure 4-4. PCI Target Read

Note: The figures represent a sequence of Bus cycles.

PCI Target PCI-to-Local Address Mapping

Five Local Address spaces—Spaces 0, 1, 2, and 3, and Expansion ROM—are accessible from the PCI Bus. Each is defined by a set of three registers:

• Local Address Range (LAS x RR and/or EROMRR, where x is the Local Address Space number)

• Local Base Address (LAS x BA and/or EROMBA)

• PCI Base Address (PCIBAR2, PCIBAR3, PCIBAR4, PCIBAR5, and/or PCIERBAR)

A fourth register, the Bus Region Descriptor registers (LAS x BRD and/or EROMBRD), defines the Local Bus characteristics for the PCI Target regions. (Refer to Figure 4-5.)

Each PCI-to-Local Address space is defined as part of reset initialization. (Refer to Section 4.2.1.8.1.) These Local Bus characteristics can be modified at any time before actual data transactions.

PCI Target Local Bus

Дата добавления: 2015-07-10