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Initialization

Читайте также:
  1. Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control

Range —Specifies the PCI Address bits to use for decoding a PCI access to Local Bus space. Each bit corresponds to a PCI Address bit. Bit 31 corresponds to address bit 31. Write 1 to all bits required to be included in decode, and 0 to all others.

Remap PCI-to-Local Addresses into a Local Address Space —Bits in this register remap (replace) the PCI Address bits used in decode as the Local Address bits.

Local Bus Region Descriptor —Specifies the Local Bus characteristics.


PCI Target Initialization

After a PCI reset and serial EEPROM load, the software determines the amount of required address space by writing all ones (1) to a PCI Base Address register and then reading back the value. The PCI 9030 returns zeros (0) in the Don’t Care Address bits, effectively specifying the address space required, at which time the PCI software maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 4-5.)



 


 

 


PCI Bus Master
   
 

 

2

Initialize PCI

Base Address Registers


Serial EEPROM


 

 

Local Address Space 0, 1, 2, and 3 Ranges
Local Address Space 0, 1, 2, and 3 Local Base Addresses (Remap)
 
Local Address Space 0, 1, 2, and 3 Bus Region Descriptors

 

Initialize Local Direct Access Registers


 

 

Expansion ROM Range
 
Expansion ROM Local Base Address (Remap)
 
Expansion ROM Bus Region Descriptor

 

Local Bus Hardware Characteristics

PCI Base Addresses for Accesses to Local Address Space 0, 1, 2, and 3
 
PCI Expansion ROM Base Address

FIFOs 32-Lword Deep Write 16-Lword Deep Read
3 4


PCI Bus

Access


Local Bus Access


 

 

 


PCI Address Space
 
 

 

PCI Base Address


 

 

Local Base Address


 

Local Memory


 

 

Range


 

 


Дата добавления: 2015-07-10; просмотров: 123 | Нарушение авторских прав


Читайте в этой же книге: Table 2-6. Burst and Bterm on the Local Bus | Table 2-8. PCI Target Single and Burst Reads | Table 2-9. Byte Number and Lane Cross-Reference | Little Endian | Table 2-14. Lower Byte Lane Transfer— 8-Bit Local Bus | Table 3-2. Serial EEPROM Register Load Sequence | Figure 3-2. PCI 9030 Internal Register Access | Timing Diagram 3-5. PCI Memory Read from Local Configuration Register | Figure 4-1. PCI Target Delayed Read Mode | Figure 4-2. PCI Target Read Ahead Mode |
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Figure 4-3. PCI Target Write| Figure 4-5. Local Bus PCI Target Access

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