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Register 10-56. (CS3BASE; 48h) Chip Select 3 Base Address

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Bit Description Read Write Value after Reset
  Chip Select 3 Enable.Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes  
  27:1 Local Base Address of Chip Select 3.Write zeros (0) in the least significant bits to define the range for Chip Select 3. Starting from bit 1 and scanning toward bit 27, the first “1” found defines size. The remaining most significant bits, excluding the first “1” found, define base address.   Yes   Yes   0h
31:28 Reserved. Yes No 0h

Notes: Chip Select 3 (CS3#) functionality of the GPIO3/CS3# multiplexed pin is enabled by configuring GPIOC[9] from the default value of 0 (GPIO3) to 1.

For a chip select to assert, the address must be encompassed within a Local Address Space.



 

CONTROL REGISTERS

Дата добавления: 2015-07-10; просмотров: 138 | Нарушение авторских прав

Читайте в этой же книге: Controlling Connection Processes CompactPCI Hot Swap | Figure 9-1. VPD Capabilities | Table 10-2. PCI Configuration Register Address Mapping | Register 10-2. (PCICR; PCI:04h) PCI Command | Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type | Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1 | Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer | Register 10-27. (PMC; PCI:42h) Power Management Capabilities | Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status | Register 10-39. (LAS1RR; 04h) Local Address Space 1 Range |
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Register 10-42. (EROMRR; 10h) Expansion ROM Range| Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control
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