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Chip Select Timing Diagrams Local Chip Selects

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  6. Local Address

 

 

5.4 CHIP SELECT TIMING DIAGRAMS

 

0ns 100ns 200ns 300ns 400ns

CLK FRAME#


AD[31:0] C/BE[3:0]#

IRDY# DEVSEL# TRDY#

 

 

LCLK


 

ADDR D0 D1 D2 D3 CMD BE


 

LREQ

 

LGNT ADS#

BLAST#

 


LA[27:2]

 

LD[31:0] READY# CS[3:0]#

LBE[3:0]#

 

WR# RD# LW/R#


ADDR +4 +8 +12 D0 D1 D2 D3

 

 

 

LBE

 

 

 

 

 

Note: CS[3:0]# Base Address is in the range of Local Address Spaces 3 through 0.

 

 

Timing Diagram 5-1. Chip Select [3:0]# (32-Bit Local Bus)


 

 


 

PCLK FRAME# AD[31:0]

CBE[3:0]#

 

IRDY# TRDY# DEVSEL#

LCLK LREQ LGNT ADS# LA[27:2]

LAD/LD[31:0] LBE[3:0]# BLAST# READY#

WR# RD# LW/R# CS[1:0]#


0ns 100ns 200ns 300ns 400ns 500ns

 

 

AD D0 D1 D2 D3 D4 D5

 

 

7 BE

 

 

 

 

 

 

 

 

 

 

+10
AD +4 +8 +C +14 AD D0 D1 D2 D3 D4 D5

BE


Note: For Multiplexed mode, use the LAD[31:0] signal for address.

For Non-Multiplexed mode, use the LA[27:2] signal for address.

 

 

Timing Diagram 5-2. PCI Target Burst Write with Delayed Write and Chip Select Enabled (32-Bit Local Bus)


 

 

6 INTERRUPTS AND GENERAL PURPOSE I/O

 


OVERVIEW

The PCI 9030 provides two Local interrupt input pins (LINTi[2:1]) and a register bit in the Interrupt Control/Status register (INTCSR[7]) that can optionally trigger PCI interrupt INTA# output. The interrupt input pins have an associated register bit to enable or disable the pin (INTCSR[3, 0], respectively), and each has a Status bit to indicate whether an interrupt source is active (INTCSR[5, 2], respectively). The LINTi[2:1] pins are programmable for active-low or active-high polarity in the default Level-Sensitive mode. They can be optionally configured as a rising edge-triggered interrupt (such as, for ISA compatibility).

Level-sensitive interrupts are cleared when the interrupt source is no longer active, or the interrupt input pin is disabled. Edge-triggered (latched) interrupts remain active until cleared by a software write, which either asserts the associated Local Edge Triggerable Interrupt Clear bit(s) (INTCSR[11:10], respectively), or disables the interrupt input pin. INTA# output can also be de-asserted by clearing the PCI Interrupt Enable bit (INTCSR[6]=0).

 

    OR    
   
   
   
   

 

INTERRUPTS

 

LINTi1

INTA#

LINTi2

 

 

Software Interrupt INTCSR[7]

 

 


Дата добавления: 2015-07-10; просмотров: 180 | Нарушение авторских прав


Читайте в этой же книге: Initialization | Figure 4-5. Local Bus PCI Target Access | Table 4-1. Response to FIFO Full or Empty | Timing Diagram 4-3. Local Edge-Triggered Interrupt Asserting PCI Interrupt | Timing Diagram 4-9. PCI Memory Write to Local Configuration Register | Timing Diagram 4-15. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State | Timing Diagram 4-17. PCI Target Burst Write (8-Bit Local Bus), No Wait States | Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only | Timing Diagram 4-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only | Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only |
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Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only| Figure 6-1. Interrupt and Error Sources

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