Timing Diagram 4-17. PCI Target Burst Write (8-Bit Local Bus), No Wait States

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PCLK FRAME# AD[31:0]

CBE[3:0]#

IRDY# TRDY# DEVSEL#

LCLK LREQ LGNT ADS# LA[27:2]

0ns 100ns 200ns 300ns 400ns

AD D0 AD D1

7 0 7 0

AD AD

LAD/LD[31:0]

AD D0

AD D1

LBE[3:0]# BLAST# READY# LW/R#

F 0 0 F

Note: For Multiplexed mode, use the LAD[31:0] signal for address.

For Non-Multiplexed mode, use the LA[27:2] signal for address.

Timing Diagram 4-18. PCI Target Back-to-Back Single Writes (32-Bit Local Bus)

PCLK FRAME# AD[31:0]

CBE[3:0]#

IRDY# TRDY# DEVSEL#

LCLK LREQ LGNT ADS#

0ns 250ns 500ns

AD D0 AD D0

7 0 6 0

LA[27:2] AD AD

LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R#

ADD0 ADD0

F 0 8 0 F

Note: For Multiplexed mode, use the LAD[31:0] signal for address.

For Non-Multiplexed mode, use the LA[27:2] signal for address.

Timing Diagram 4-19. PCI Target Back-to-Back Burst Write Followed by Read (16-Bit Local Bus)

PCLK FRAME# AD[31:0]

CBE[3:0]#

IRDY# TRDY# DEVSEL#

LCLK LREQ LGNT ADS# LA[27:2]

LAD/LD[31:0] LBE[3:0]# BLAST# READY# LW/R#

0ns 250ns 500ns 750n

AD D0 AD D1

6 0 7 0

AD AD

AD DO AD DO

F 0 F 0 F

Note: For Multiplexed mode, use the LAD[31:0] signal for address.

For Non-Multiplexed mode, use the LA[27:2] signal for address.

Timing Diagram 4-20. PCI Target Back-to-Back Burst Read Followed by Write (16-Bit Local Bus)

PCLK FRAME# AD[31:0]

CBE[3:0]#

IRDY# TRDY# DEVSEL#

LCLK LREQ LGNT ADS#

0ns 250ns 500ns 750ns

AD D0 AD D1 6 0 6

LA[27:2] LAD/LD[31:0]

AD O

LBE[3:0]# BLAST# READY# LW/R#

F 0 F 0 F

Note: For Multiplexed mode, use the LAD[31:0] signal for address.

For Non-Multiplexed mode, use the LA[27:2] signal for address.

Timing Diagram 4-21. PCI Target Back-to-Back Burst Reads (16-Bit Local Bus)

Multiplexed Mode Only Timing Diagrams

0ns 250ns 500ns

CLK FRAME# AD[31:0] C/BE[3:0]#

IRDY# DEVSEL# TRDY#

LCLK LREQ LGNT ADS# ALE BLAST# LBE[3:0]# LW/R# LAD[31:0]

READY# (input)

1 2 3

ADDR

CMD

Data

5 6 7 8

LBE

A Data

Timing Diagram 4-22. PCI Target Single Write (32-Bit Local Bus), Multiplexed Mode Only

0ns 100ns 200ns 300ns 400ns 500n

CLK FRAME# AD[31:0] C/BE[3:0]#

IRDY# DEVSEL# TRDY#

LCLK LREQ LGNT ADS# ALE BLAST# LW/R# LBE[3:0]#

LAD[31:0]

READY# (input)

1 2 3

ADDR

CMD

4 5 6 7 8

LBE

A Data

Data

Дата добавления: 2015-07-10; просмотров: 147 | Нарушение авторских прав

Читайте в этой же книге: Figure 3-2. PCI 9030 Internal Register Access | Timing Diagram 3-5. PCI Memory Read from Local Configuration Register | Figure 4-1. PCI Target Delayed Read Mode | Figure 4-2. PCI Target Read Ahead Mode | Figure 4-3. PCI Target Write | Initialization | Figure 4-5. Local Bus PCI Target Access | Table 4-1. Response to FIFO Full or Empty | Timing Diagram 4-3. Local Edge-Triggered Interrupt Asserting PCI Interrupt | Timing Diagram 4-9. PCI Memory Write to Local Configuration Register |

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Timing Diagram 4-15. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State	\|	Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only

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