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0ns 50ns 100ns 150ns 200ns 250ns
CLK FRAME# AD[31:0] C/BE[3:0]#
IRDY# DEVSEL# TRDY#
1 2 3
ADDR CMD=6
4 5 6 7 8
Data Read
BE
Timing Diagram 4-10. PCI Memory Read from Local Configuration Register
Multiplexed and Non-Multiplexed Modes Timing Diagrams
PCLK FRAME# AD[31:0]
CBE[3:0]#
IRDY# TRDY# DEVSEL#
LCLK LREQ LGNT ADS# LA[27:2]
LAD/LD[31:0] LBE[3:0]# BLAST# READY#
WR# RD# LW/R# CS[1:0]#
0ns 100ns 200ns 300ns 400ns 500ns
AD D0 D1 D2 D3 D4 D5
7 BE
+10 |
BE
Note: For Multiplexed mode, use the LAD[31:0] signal for address.
For Non-Multiplexed mode, use the LA[27:2] signal for address.
Timing Diagram 4-11. PCI Target Burst Write with Delayed Write and Chip Select Enabled (32-Bit Local Bus)
PCLK FRAME# AD[31:0]
CBE[3:0]#
IRDY# TRDY# DEVSEL#
LCLK LREQ LGNT ADS# LA[27:2]
LAD/LD[31:0] LBE[3:0]# BLAST# READY#
WR# RD# LW/R#
0ns 250ns 500ns
AD D0 D1 D2 D3 7 0
AD
AD D0 D1 D2 D3
F 0 F
Note: For Multiplexed mode, use the LAD[31:0] signal for address.
For Non-Multiplexed mode, use the LA[27:2] signal for address.
Five Address-to-Data Wait States; One Data-to-Data Wait State; Three Write Strobe Delay Clocks; Two Write Cycle Hold Clocks.
Timing Diagram 4-12. PCI Target Burst Write (32-Bit Local Bus)
PCLK FRAME# AD[31:0]
CBE[3:0]#
IRDY# TRDY# DEVSEL#
LCLK LREQ LGNT ADS# LA[27:2]
LAD/LD[31:0] LBE[3:0]# BLAST# READY#
WR# RD# LW/R#
0ns 100ns 200ns 300ns 400ns
AD D0 D1 D2 D3 D4 D5 7 0
AD AD
F 4 6 4 6 4 6 4 6 4 6 4 6
Note: For Multiplexed mode, use the LAD[31:0] signal for address.
For Non-Multiplexed mode, use the LA[27:2] signal for address.
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Timing Diagram 4-3. Local Edge-Triggered Interrupt Asserting PCI Interrupt | | | Timing Diagram 4-15. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State |