Table 4-1. Response to FIFO Full or Empty

Mode	Direction	FIFO	PCI Bus	Local Bus
PCI Target Write	PCI-to-Local	Full	Disconnect or Throttle TRDY#1	If CNTRL[31]=0 (default preempt condition), de-assert LGNT if the Local Bus is busy. In either case, wait for LREQ to be de-asserted by the local bus master.
Empty	Normal	Normal, assert BLAST#.
PCI Target Read	Local-to-PCI	Full	Normal	Normal, assert BLAST#.
Empty	Disconnect or Throttle TRDY#1	Normal.

1. Throttle TRDY# depends on the PCI Target Retry Delay Clocks (CNTRL[22:19]).

PCI TARGET (DIRECT SLAVE) OPERATION TIMING DIAGRAMS

0ns 250ns 500ns

LCLK LREQ LGNT

Local Bus is requested by another Local Initiator.

PCI 9030 grants the Local Bus to another Local Initiator; otherwise, remains low.

Local Bus

Another Local Initiator Drives Bus

De-asserted if PCI 9030 needs to use a Local Bus and CNTRL[7]=0; otherwise, remains high until the Local Initiator is done.

Timing Diagram 4-1. Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT)

CLK FRAME#

0ns 100ns 200ns 300ns 400ns 500ns

AD[31:0]

ADDR

DATA

C/BE[3:0]#

IRDY# DEVSEL# TRDY#

INTA#

LCLK LINTi[2:1]

CMD BE

1 2

INTA# assertion is asynchronous to both PCI and Local clocks.

Дата добавления: 2015-07-10