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Timing Diagram 4-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only

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  6. Figure 4-1. PCI Target Delayed Read Mode
  7. Figure 4-2. PCI Target Read Ahead Mode

 

0ns 250ns 500ns

 


 

CLK FRAME#


 

 

1 2 3 4


 

 

5 6 7 8


AD[31:0] C/BE[3:0]#

IRDY# DEVSEL# TRDY#

 

 

LCLK LREQ LGNT ADS# BLAST# LBE[3:0]#

LW/R# LA[27:2]


ADDR

 

 

CMD


DO D1 D3 D4

 

 

BE


 

A +4


 

 

LBE

 

+8 +C +10


LD[31:0]

 

READY# (input)


D0 D1 D2 D3 D4


 

Five Lwords, one external wait state, Bterm enabled, Burst enabled.

 

Timing Diagram 4-36. PCI Target Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only


 


 

CLK FRAME#


0ns 250ns 500ns 750ns 1000ns


AD[31:0] A A


A D0 D1 D2 D3 D4 D5 D6 D7 D8


ADDR D0


 


C/BE[3:0]#

 

IRDY# DEVSEL# TRDY# STOP#

 

 

LCLK


CMD BE

 

Retry

 

 

Delayed Read Retries


CMD BE

 

Retry

 

 

Write Is Not Allowed During Delayed Read


CMD


BE

 

Reads Data


 

 

Write Retries and Completes


CMD


 

LREQ

 

LGNT ADS#

BLAST#

 


LBE[3:0]#

 

LW/R# LA[27:2]

LD[31:0]

 

READY# (input)


LBE

 

 

ADDR +4 +8 +C +10+14+18+1C+20+24+28+2C+30+34+38+3C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15

 

Disconnect immediately for a read. Does not affect pending reads when a Write cycle occurs, nor flush the Read FIFO if the PCI Read cycle completes.

 

When a read is pending, force Retry on a write. De-assert TRDY# until space is available in the


 

Дата добавления: 2015-07-10; просмотров: 153 | Нарушение авторских прав

Читайте в этой же книге: Figure 4-1. PCI Target Delayed Read Mode | Figure 4-2. PCI Target Read Ahead Mode | Figure 4-3. PCI Target Write | Initialization | Figure 4-5. Local Bus PCI Target Access | Table 4-1. Response to FIFO Full or Empty | Timing Diagram 4-3. Local Edge-Triggered Interrupt Asserting PCI Interrupt | Timing Diagram 4-9. PCI Memory Write to Local Configuration Register | Timing Diagram 4-15. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State | Timing Diagram 4-17. PCI Target Burst Write (8-Bit Local Bus), No Wait States |
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Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only| Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only
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