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Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only

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  3. Chip Select Timing Diagrams Local Chip Selects
  4. Figure 2-1. Local Bus Block Diagram
  5. Figure 4-1. PCI Target Delayed Read Mode
  6. Figure 4-2. PCI Target Read Ahead Mode
  7. Figure 4-3. PCI Target Write

 

0ns 100ns 200ns 300ns 400ns 500ns

 


 

CLK FRAME#


 

 

1 2 3


 

 

4 5 6 7 8


AD[31:0] C/BE[3:0]#

IRDY# DEVSEL#

TRDY#

 

LCLK LREQ LGNT ADS# BLAST# LBE[3:0]#

LW/R# LA[27:2]


ADDR

 

 

CMD


Data= AABBCCDD

 

BE



 

 

ADDR


 

LBE


LD[31:0]


DDCCBBAA 67452301


 

READY# (input)

 

Timing Diagram 4-40. PCI Target Write to Local Target in BIGEND Mode, Non-Multiplexed Mode Only


 


 

 


5 LOCAL CHIP SELECTS

OVERVIEW

The PCI 9030 provides four chip select outputs to selectively enable devices on its Local Bus. Each active-low chip select is programmable and independent of any local address space. Without this feature, external address decoding logic is required to implement chip selects.

 

CHIP SELECT BASE ADDRESS REGISTERS

There are four Chip Select Base Address registers. These registers control the four chip select pins on the PCI 9030. [ For example, Chip Select 0 Base Address register (CS0BASE) controls CS0#, Chip Select 1 Base Address register (CS1BASE) controls CS1#, and so forth.]

The Chip Select Base Address registers serve three purposes:

1. To enable or disable chip select functions within the PCI 9030. If enabled, the chip select signal is active if the Local Bus Address falls within the address specified by the range and base address. If disabled, the chip select signal

is not active.

 

2. To set the range of the Local Bus Addresses for which the chip select signal(s) is active.

 

3. To set the Local Base Address, at which the range starts.


 

Chip selects are not bound to any particular Local Address Space unless programmed accordingly in the CS x BASE, LAS x RR, and LAS x BA registers (where x is the Chip Select number or Local Address Space number,

as appropriate).

Each 28-bit Chip Select Base Address register is programmed, as listed in the following table.

 

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Читайте в этой же книге: Figure 4-3. PCI Target Write | Initialization | Figure 4-5. Local Bus PCI Target Access | Table 4-1. Response to FIFO Full or Empty | Timing Diagram 4-3. Local Edge-Triggered Interrupt Asserting PCI Interrupt | Timing Diagram 4-9. PCI Memory Write to Local Configuration Register | Timing Diagram 4-15. PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State | Timing Diagram 4-17. PCI Target Burst Write (8-Bit Local Bus), No Wait States | Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only | Timing Diagram 4-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only |
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Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only| Chip Select Timing Diagrams Local Chip Selects
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