Figure 9-1. VPD Capabilities

VPD SERIAL EEPROM PARTITIONING

To support VPD, the serial EEPROM is partitioned into read-only and read/write sections.

SEQUENTIAL READ ONLY

The first 1088 bits (136 bytes) of the serial EEPROM contain read-only information. The read-only portion of the serial EEPROM is loaded into the PCI 9030, using a sequential read protocol to the serial EEPROM and occurs after PCI reset. Sequential words are read by holding EECS asserted, following issuance of a serial EEPROM Read command.

RANDOM ACCESS READ AND WRITE

The PCI 9030 has full access to the read/write portion of the serial EEPROM. The serial EEPROM, starting at Lword Boundary for VPD Accesses bits (PROT_AREA[6:0]), designates this portion. This register is loaded upon power-on and can be written with a desired value, starting at location 0. This provides the capability of writing the entire serial EEPROM. Writes to the serial EEPROM are comprised of the following commands:

• Write Enable

• Write command, followed by the upper 16-bit Write data

• Write command, followed by the lower 16-bit Write data

• Write Disable

This is done to ensure against accidental write of the serial EEPROM. Randomly occurring cycles allow VPD information to be written and read at any time.

To perform a simple VPD write to the serial EEPROM, the following steps are necessary:

1. Change the write-protected serial EEPROM address in PROT_AREA[6:0], if required. 00000000h makes the serial EEPROM writable from the beginning.

2. Write the desired data into the PVPDATA register.

3. Write the destination serial EEPROM address and flag of operation to a value of 1.

4. Probe the flag of operation until it changes to a 0 to ensure the write is complete.

To perform a simple VPD read from the serial EEPROM, the following steps are necessary:

1. Write a destination serial EEPROM address and flag of operation to a value of 0.

2. Probe the flag of operation until it changes to a 1 to ensure the Read data is available.

3. Read back the PVPDATA register to see the requested data.

10 REGISTERS

NEW REGISTER DEFINITIONS SUMMARY

(AS COMPARED TO THE PCI 9050 AND PCI 9052)

Refer to the description column in the following tables for a full explanation.

Table 10-1. New Registers Definitions Summary (As Compared to the PCI 9050 and PCI 9052)

PCI Register Address	Local Offset from Base Address	Register	Bits	Description
34h	—	New Capability Pointer	7:0	Provides offset into PCI Configuration space for the location of the first item in the New Capability Linked List.
40h	—	Power Management	31:0	Provides Power Management ID, Power Management Next Capability Pointer, and Power Management Capabilities.
44h	—	Power Management	31:0	Provides Power Management Status, PMCSR Bridge Support Extensions, and Power Management Data.
48h	—	CompactPCI Hot Swap	31:0	Hot Swap Control, Hot Swap Next Capability Pointer, and Hot Swap Control/Status Register.
4Ch	—	PCI Vital Product Data	31:0	VPD ID, VPD Next Capability Pointer, and VPD Address Pointer.
50h	—	PCI Vital Product Data	31:0	VPD Data.
—	4Eh	Serial EEPROM Write-Protected Address Boundary	6:0 15:7	Serial EEPROM Write-Protected Address Boundary. Reserved.
—	50h	PCI Target Response, Serial EEPROM, and Initialization Control	5:0 11:10	Reserved. PCI Target Write FIFO Full Condition. Local Arbiter LGNT Select Enable. Local Ready Timeout Enable. Local Ready Timeout Select. PCI Target Delayed Write Mode Access Select. Disconnect with Flush Read FIFO.
—	54h	General Purpose I/O Control	26:0 31:27	GPIO[8:0] Control Select bits. Reserved.
—	70h	Hidden 1 Power Management Data Select	31:0	Data Select register for Power Consumed and Dissipated. Written only by the serial EEPROM.
—	74h	Hidden 2 Power Management Data Scale	7:0   31:8	Data Scale Factor Values for Power Consumed and Dissipated. Written only by the serial EEPROM. Reserved.

REGISTER ADDRESS MAPPING

Дата добавления: 2015-07-10