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Table 10-2. PCI Configuration Register Address Mapping

Читайте также:
  1. Address
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  3. CONTEXT AND REGISTER
  4. Countable and uncountable nouns (Существительные исчисляемые и неисчисляемые).
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  7. Fill in the blanks with the suitable words.

 

PCI Configuration Register Address To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits.   31 30 24 23 16 15 8 7 0     PCI Writable   Serial EEPROM Writable
00h Device ID Vendor ID N Y
04h Status Command Y Y [20]
08h Class Code Revision ID N Y
  0Ch Built-In Self Test (Not Supported)   Header Type PCI Bus Latency Timer (Not Supported)   Cache Line Size Y [7:0]   N
10h PCI Base Address 0 for Memory Accesses to Local Configuration Registers Y N
14h PCI Base Address 1 for I/O Accesses to Local Configuration Registers Y N
18h PCI Base Address 2 for Accesses to Local Address Space 0 Y N
1Ch PCI Base Address 3 for Accesses to Local Address Space 1 Y N
20h PCI Base Address 4 for Accesses to Local Address Space 2 Y N
24h PCI Base Address 5 for Accesses to Local Address Space 3 Y N
28h PCI Cardbus Information Structure (CIS) Pointer (Not Supported) N N
2Ch Subsystem ID Subsystem Vendor ID N Y
30h PCI Base Address for Local Expansion ROM Y N
34h Reserved New_Cap Pointer N Y [7:0]
38h Reserved N N
3Ch Maximum Latency (Not Supported) Minimum Grant (Not Supported) Interrupt Pin Interrupt Line Y [7:0] Y [15:8]
  40h   Power Management Capabilities Power Management Next_Cap Pointer Power Management Capability ID   N Y [30:27, 21, 19:16, 15:8]
  44h   Power Management Data PMCSR Bridge Support Extensions   Power Management Control/Status Y [15, 12:8, 1:0] Y [12:8]
48h Reserved Hot Swap Control/Status Hot Swap Next_Cap Pointer Hot Swap Capability ID Y [23:16] Y [15:0]
4Ch F VPD Address VPD Next_Cap Pointer VPD Capability ID Y [31:16] Y [15:8]
50h VPD Data Y N
               

 

Note: Refer to PCI r2.2 for definitions of these registers.



 

 

Table 10-3. Local Configuration Register Address Mapping

 

PCI (Offset from Base Address) To ensure software compatibility with other versions of the PCI 9030 family and to ensure compatibility with future enhancements, write 0 to all unused bits.   31 0     PCI Writable   Serial EEPROM Writable
00h Local Address Space 0 Range Y Y
04h Local Address Space 1 Range Y Y
08h Local Address Space 2 Range Y Y
0Ch Local Address Space 3 Range Y Y
10h Expansion ROM Range Y Y
14h Local Address Space 0 Local Base Address (Remap) Y Y
18h Local Address Space 1 Local Base Address (Remap) Y Y
1Ch Local Address Space 2 Local Base Address (Remap) Y Y
20h Local Address Space 3 Local Base Address (Remap) Y Y
24h Expansion ROM Local Base Address (Remap) Y Y
28h Local Address Space 0 Bus Region Descriptor Y Y
2Ch Local Address Space 1 Bus Region Descriptor Y Y
30h Local Address Space 2 Bus Region Descriptor Y Y
34h Local Address Space 3 Bus Region Descriptor Y Y
38h Expansion ROM Bus Region Descriptor Y Y

 

 

Дата добавления: 2015-07-10; просмотров: 149 | Нарушение авторских прав

Читайте в этой же книге: Timing Diagram 4-17. PCI Target Burst Write (8-Bit Local Bus), No Wait States | Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only | Timing Diagram 4-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only | Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only | Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only | Chip Select Timing Diagrams Local Chip Selects | Figure 6-1. Interrupt and Error Sources | Timing Diagram 6-3. GPIO[8:0] as Outputs | System Changes Power Mode Example PCI Power Management | Controlling Connection Processes CompactPCI Hot Swap |
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Figure 9-1. VPD Capabilities| Register 10-2. (PCICR; PCI:04h) PCI Command
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