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Bit | Description | Read | Write | Value after Reset |
Memory Space Indicator.Writing 0 indicates Local Address Space 1 maps into PCI Memory space. Writing 1 indicates Local Address Space 1 maps into PCI I/O space. | Yes | Yes | ||
2:1 | When mapped into Memory space, encoding is as follows: 00 = Locate anywhere in 32-bit PCI Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit PCI Address space 11 = Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. | Yes | Yes | |
When mapped into Memory space, writing 1 indicates reads are prefetchable (does not affect PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. | Yes | Yes | ||
27:4 | Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 1. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR3). Notes: Range (notRange register) must be power of 2. “Range register value” is two’s complement of range. User should limit each I/O-mapped space to 256 bytes per PCI r2.2. | Yes | Yes | 0h |
31:28 | Reserved. (PCI Address bits [31:28] are always included in decoding.) | Yes | No | 0h |
Register 10-40. (LAS2RR; 08h) Local Address Space 2 Range
Bit | Description | Read | Write | Value after Reset |
Memory Space Indicator.Writing 0 indicates Local Address Space 2 maps into PCI Memory space. Writing 1 indicates Local Address Space 2 maps into PCI I/O space. | Yes | Yes | ||
2:1 | When mapped into Memory space, encoding is as follows: 00 = Locate anywhere in 32-bit PCI Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit PCI Address space 11 = Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range. | Yes | Yes | |
When mapped into Memory space, writing 1 indicates reads are prefetchable (does not affect PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range. | Yes | Yes | ||
27:4 | Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 2. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR4). Notes: Range (notRange register) must be power of 2. “Range register value” is two’s complement of range. User should limit each I/O-mapped space to 256 bytes per PCI r2.2. | Yes | Yes | 0h |
31:28 | Reserved. (PCI Address bits [31:28] are always included in decoding.) | Yes | No | 0h |
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Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status | | | Register 10-42. (EROMRR; 10h) Expansion ROM Range |