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Register 10-39. (LAS1RR; 04h) Local Address Space 1 Range

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Bit Description Read Write Value after Reset
  Memory Space Indicator.Writing 0 indicates Local Address Space 1 maps into PCI Memory space. Writing 1 indicates Local Address Space 1 maps into PCI I/O space.   Yes   Yes  
    2:1 When mapped into Memory space, encoding is as follows: 00 = Locate anywhere in 32-bit PCI Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit PCI Address space 11 = Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range.     Yes     Yes    
  When mapped into Memory space, writing 1 indicates reads are prefetchable (does not affect PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range.   Yes   Yes  
  27:4 Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 1. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR3). Notes: Range (notRange register) must be power of 2. “Range register value” is two’s complement of range. User should limit each I/O-mapped space to 256 bytes per PCI r2.2.   Yes   Yes   0h
31:28 Reserved. (PCI Address bits [31:28] are always included in decoding.) Yes No 0h


 

 

Register 10-40. (LAS2RR; 08h) Local Address Space 2 Range

 

Bit Description Read Write Value after Reset
  Memory Space Indicator.Writing 0 indicates Local Address Space 2 maps into PCI Memory space. Writing 1 indicates Local Address Space 2 maps into PCI I/O space.   Yes   Yes  
    2:1 When mapped into Memory space, encoding is as follows: 00 = Locate anywhere in 32-bit PCI Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit PCI Address space 11 = Reserved When mapped into I/O space, bit 1 must be set to 0. Bit 2 is included with bits [27:3] to indicate the decoding range.     Yes     Yes    
  When mapped into Memory space, writing 1 indicates reads are prefetchable (does not affect PCI 9030 operation, but is used for system status). When mapped into I/O space, it is included with bits [27:2] to indicate the decoding range.   Yes   Yes  
  27:4 Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 2. Each bit corresponds to a PCI Address bit. Bit 27 corresponds to address bit 27. Write 1 to all bits that are to be included in decode and 0 to all others (used in conjunction with PCIBAR4). Notes: Range (notRange register) must be power of 2. “Range register value” is two’s complement of range. User should limit each I/O-mapped space to 256 bytes per PCI r2.2.   Yes   Yes   0h
31:28 Reserved. (PCI Address bits [31:28] are always included in decoding.) Yes No 0h

 


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Читайте в этой же книге: Timing Diagram 6-3. GPIO[8:0] as Outputs | System Changes Power Mode Example PCI Power Management | Controlling Connection Processes CompactPCI Hot Swap | Figure 9-1. VPD Capabilities | Table 10-2. PCI Configuration Register Address Mapping | Register 10-2. (PCICR; PCI:04h) PCI Command | Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type | Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1 | Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer | Register 10-27. (PMC; PCI:42h) Power Management Capabilities |
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Register 10-33. (HS_CSR; PCI:4Ah) Hot Swap Control/Status| Register 10-42. (EROMRR; 10h) Expansion ROM Range

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