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Table 13-2. Symbol Definitions—PQFP Package

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Symbol Term Definition Symbol Term Definition
  E   Package width   Width of package   C   Lead thickness Thickness of lead (excluding surface plating)
  D   Package length   Length of package q   Lead angle Angle of leads versus seating plane
  A   Mounting height Height from the ground plane to the top of the package q2, q3   Chamfer angle   Package chamfer angle
  A1   Standoff height Height from the ground plane to the bottom edge of the package (PGA)   L, L1, L2   Lead length or length of flat lead section   Lead length or length of flat lead section
  A2   Package height Height of the package (excluding warp of package) HE   Overall width   Width including leads
e Linear lead pitch Theoretical lead pitch HD Overall length Length
  b   Lead width Lead width or diameter (excluding surface plating)   R, R1   Reverse bending   Reverse bending type

 


Pad Width 0.3048 mm


Fiducial


 

Metal Pad

1.016 mm


 


Pad Length

1.524 mm


 

Solder Mask Keepout Area


 

 

2.54 mm


 

 

B = 27.178 mm

 

 

Fiducial

 

Pad Pitch = 0.500 mm A = 27.178 mm

Figure 13-2. 176-Pin PQFP PCB Layout Suggested Land Pattern


 

 


 

    VDD     VDD  
GPIO7/LA24 GPIO7/LA24  
GPIO6/LA25 GPIO6/LA25  
GPIO5/LA26 GPIO5/LA26  
GPIO4/LA27 GPIO4/LA27  
ADS# ADS#  
BLAST# BLAST#  
WR# WR#  
RD# RD#  
LW/R# LW/R#  
READY# READY#  
BTERM# BTERM#  
LCLK LCLK  
VSS VSS  
CS0# CS0#  
CS1# CS1#  
LRESETo# LRESETo#  
LGNT LGNT  
LREQ LREQ  
LINTi1 LINTi1  
LINTi2 LINTi2  
GPIO0/WAITo# GPIO0/WAITo#  
GPIO1/LLOCKo# GPIO1/LLOCKo#  
GPIO2/CS2# GPIO2/CS2#  
GPIO3/CS3# GPIO3/CS3#  
EECS EECS  
EEDO EEDO  
EESK EESK  
EEDI EEDI  
VDD VDD  
VSS VSS  
TRST# TRST#  
TCK TCK  
TMS TMS  
TDO TDO  
TDI TDI  
PME# PME#  
INTA# INTA#  
RST# RST#  
PCLK PCLK  
AD31 AD31  
AD30 AD30  
     

 

AD29 VSS


 

AD29 VSS


 


 

 


Дата добавления: 2015-07-10; просмотров: 145 | Нарушение авторских прав


Читайте в этой же книге: Register 10-56. (CS3BASE; 48h) Chip Select 3 Base Address | Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control | Register 10-60. (GPIOC; 54h) General Purpose I/O Control | Register 10-61. (PMDATASEL; 70h) Hidden 1 Power Management Data Select | Table 11-2. Input Pin Pull-Up and Pull-Down Resistor Requirements | Pull-Up and Pull-Down Resistor Recomme Pin Description | Table 11-8. Test and Debug Pins | Table 11-11. Multiplexed Bus Mode Interface Pins | Table 12-5. Electrical Characteristics over Operating Range | Table 12-6. AC Electrical Characteristics (Local Inputs) over Operating Range |
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Table 12-7. AC Electrical Characteristics (Local Outputs) over Operating Range| Table 13-4. Symbol Definitions—µBGA Package

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