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Signals (Synchronous Inputs) CL= 50 pF, VCC= 3.0V, Ta = 85 °C | Bus Mode | TSETUP(ns) (Worst Case) | THOLD(ns) (Worst Case) |
BTERM# | All | 7.0 | |
LAD[31:0] (Data) | Multiplexed | 5.0 | |
LD[31:0] | Non-Multiplexed | 5.0 | |
LPMESET | All | 5.0 | |
LREQ | All | 5.0 | |
READY# | All | 7.0 | |
Input Clocks | Bus Mode | Min | Max |
Local Clock Input Frequency | All | 60 MHz | |
PCI Clock Input Frequency | All | 33 MHz |
Note: These values are provided as an example and are only representative of PLX PCI device general performance characteristics.
LOCAL OUTPUTS
Definition:
• TVALID —Output valid (clock-to-out). The time after the rising edge of the Local Clock until the output is stable.
Local Clock
T
VA L I D (MAX)
Outputs
T
VA L I D (MIN)
Valid
Figure 12-2. PCI 9030 Local Output Delay
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Table 12-5. Electrical Characteristics over Operating Range | | | Table 12-7. AC Electrical Characteristics (Local Outputs) over Operating Range |