Local chip selects

See chip select

lock 4-1

atomic operations 11-9

CNTRL 10-35

cycles 1-5

LLOCKo# 2-4, 11-3, 11-9, 13-3, 13-6

LOCK# 10-35, 11-7, 13-3, 13-6

PCI Target enable 10-35

LOCK# 10-35, 11-7, 13-3, 13-6

LPMESET 11-2, 11-11, 13-3, 13-6

LPMINT# 6-2, 11-11, 13-3, 13-6

LREQ 2-5, 11-2, 11-11, 13-3, 13-6

LRESETo# 3-1, 11-11, 13-3, 13-6

LW/R# 2-4, 11-14, 11-16, 13-3, 13-6

M

Map

memory 5-2

PCI software 4-5

PCI Target 1-3

read accesses 4-4

registers 3-7

serial EEPROM memory 3-2

See Also mapping and remap

Mapping

address 4-3

expansion ROM local base address register 10-20

local address space local base address registers 10-19– 10-20

local registers 4-1

memory, prefetchable 2-1–2-2

register address 10-2–10-3 Master Abort, not supported 10-5 maximum ratings 12-1

Memory

accesses 2-9, 3-6, 3-7, 10-2, 10-7, 10-8, 10-9

address spaces 10-16, 10-17, 10-19, 10-20

BTERM# 2-9

burst memory-mapped 1-3 commands aliased to basic 2-1 cycle 3-7

disabled 7-1

local controller 2-8

local spaces 1-3

map example 5-2

mapping, prefetchable 2-1–2-2

PCI 4-4, 7-2, 10-13

posted writes (PMW) 1-3 read 2-1, 4-4

µBGA

to PCI r2.2

cycle 10-21, 10-23, 10-25, 10-27, 10-29

serial EEPROM map 3-2 timing diagrams 3-10, 4-15

write 2-1, 10-4

BGA

product ordering and support A-1 layers, routing 13-7–13-8

package mechanical dimensions 13-4 PCB layout suggested land pattern 13-5 pinout 13-6

MODE 11-2, 11-11, 13-3, 13-6

Modes, bus

See Multiplexed mode and Non-Multiplexed mode

Multiplexed mode 11-2, 11-7, 11-9–11-11

Bus mode 11-12–11-14

byte number and lane cross-reference 2-11 interface pin 11-1

Local Bus 1-3, 2-6 programmable Local Bus 1-3 recovery states 2-10

timing diagrams 4-9–4-31

N

NC (µBGA) 11-4, 13-6

networking 1-1

New capabilities

functions support 10-5

linked list 7-1

Next_Cap Pointer 8-4

Pointer (CAP_PTR) 7-1, 10-1, 10-10

structure 3-7, 8-4, 9-1

support bit 7-1

VPD 9-1

Non-burst

See burst

Non-Multiplexed mode 11-9–11-11 Big/Little Endian byte number and lane

cross-reference 2-11

Bus mode 11-15–11-17

interface pin 11-1

Local Bus 1-3, 2-6

programmable Local Bus modes 1-3 recovery states 2-10

timing diagrams 4-9–4-26, 4-32–4-45

NRAD, NRDD, NWAD, NWDD, and NXDA 2-8, 10-21– 10-29

See Also internal wait states

O

operating ranges 12-1

Дата добавления: 2015-07-10