Reconfiguration, system

See configuration

recovery states 2-3, 2-10

register addresses 1-5, 10-2–10-3

Registers

CAP_PTR 3-3, 3-7, 7-1, 10-10

CNTRL 1-5, 2-5, 3-1, 3-4, 4-1, 4-2, 4-4, 4-8, 10-34–10-35

CS0BASE 3-4, 10-31

CS1BASE 3-4, 10-31

CS2BASE 3-4, 10-32

CS3BASE 3-4, 10-32

EROMBA 3-4, 4-4, 10-20

EROMBRD 3-4, 4-5, 10-29

EROMRR 3-3, 4-4, 10-10, 10-18

GPIOC 6-3, 10-36–10-37

HS_CNTL 3-3, 8-4, 10-14

HS_CSR 1-2, 8-1, 8-3, 10-14

HS_NEXT 3-3, 3-7, 8-4, 10-14

INTCSR 3-4, 6-2, 10-33

LAS0BA 3-3, 4-4, 4-7, 10-8, 10-19

LAS0BRD 2-8, 3-4, 4-3, 4-5, 10-21

LAS0RR 3-3, 4-4, 10-8, 10-16

LAS1BA 3-4, 4-4, 4-7, 10-8, 10-19

LAS1BRD 2-8, 3-4, 4-3, 4-5, 10-23

LAS1RR 3-3, 4-4, 10-8, 10-16

LAS2BA 3-4, 4-4, 10-9, 10-20

LAS2BRD 2-8, 3-4, 4-3, 4-5, 10-25

LAS2RR 3-3, 4-4, 10-9, 10-17

LAS3BA 3-4, 4-4, 10-9, 10-20

LAS3BRD 2-8, 3-4, 4-3, 4-5, 10-27

LAS3RR 3-3, 4-4, 10-9, 10-17

PCIBAR0 3-7, 4-4, 10-7

PCIBAR1 3-7, 4-4, 10-7

PCIBAR2 4-4, 10-8

PCIBAR3 4-4, 10-8

PCIBAR4 4-4, 10-9

PCIBAR5 4-4, 10-9

PCIBISTR (not supported) 10-6 PCICCR 3-3, 10-5

PCICIS (not supported) 10-10 PCICLSR 3-6, 10-6

PCICR 6-2, 10-4

PCIERBAR 3-7, 4-4, 10-10

PCIHTR 3-6, 10-6

PCIIDR 3-3, 10-4

PCIILR 3-3, 10-11

PCIIPR 3-3, 10-11

PCILTR (not supported) 10-6 PCIMGR (not supported) 10-11

registers, hidden (PMDATASEL, PMDATASCALE)

to system reconfiguration

PCIMLR (not supported) 10-11 PCIREV 3-3, 10-5

PCISID 3-3, 10-10

PCISR 3-3, 7-1, 10-5

PCISVID 3-3, 10-4, 10-10

PMC 3-3, 3-5, 7-2, 10-12

PMCAPID 3-3, 7-1, 10-12

PMCSR 3-3, 3-5, 6-2, 7-2, 7-3, 10-1, 10-2, 10-13, 10-14,

10-37, 11-11

PMCSR_BSE 10-13

PMDATA 3-5, 7-2, 7-3, 10-14, 10-37

PMDATASCALE 7-2, 7-3, 10-13, 10-37

PMDATASEL 7-2, 7-3, 10-14, 10-37

PMNEXT 3-3, 3-7, 7-1, 10-12

PROT_AREA 3-4, 9-2, 10-33

PVPD_NEXT 3-3, 3-7, 9-1, 10-15

PVPDAD 9-1, 10-15

PVPDATA 9-1, 10-15

PVPDCNTL 3-3, 9-1, 10-15

registers, hidden (PMDATASEL, PMDATASCALE)

7-2–7-3, 10-37

registers, new definitions summary 10-1

Remap

local base address 4-7

PCI-to-Local addresses 4-5

serial EEPROM register load sequence 3-3

See Also map and mapping

Reset

initialization 4-5

platform 8-2

serial EEPROM 3-1–3-10

soft 7-1, 7-2

software 3-1, 10-35

resistors 8-1, 11-1–11-3 retry delay timer 4-4 Revision ID 3-6, 10-5

RISC architecture 2-2

routing, board, µBGA 13-7–13-8

RST# 3-1, 11-8, 13-3, 13-6

S

Serial EEPROM

accidental write to 9-2 CNTRL register 10-34–10-35

control 10-3

device ID and vendor ID registers 10-4 interface 1-4

interface pins 11-1, 11-5 internal registers access 2-6 PROT_AREA 10-33

random read and write 9-2 read control 1-5

read-only portion 9-1

reset and initialization 3-1–3-10 support 1-5

timing diagrams 4-13–4-15

vendor ID and device ID registers 10-4 VPD 9-1–9-2

write 9-2, 10-5, 10-10, 10-11, 10-14, 10-15, 10-18

Write-Protected Address Boundary register (PROT_AREA) 10-1, 10-3, 10-33

SERR# 11-8, 13-3, 13-6

setup and hold waveform, local input 12-3

Дата добавления: 2015-07-10