Lab13: Study of Dynamic Shift Register

Digital Integrated Circuits

Objective

To study the properties of dynamic shift register as well as their characteristics and parameters by the application of HSPICE circuit simulation tool and hence provide an estimation of its values through calculations

Laboratory tasks

2.1. Characteristics of Dynamic Shift Register (DSHRG4) Circuit

• Build the circuit of 4-bit dynamic shift register based on data of table 1 (Fig.13.1) using Fig. 13.2.

Fig. 13.1. 4-bit dynamic shift register’s logic circuit and input and output signal waveforms

Truth table of 4-bit shift register

CLK1	CLK2	D	Q0	Q1	Q2	Q3
		D0
I clock pulse	I clock pulse	D1	D1
II clock pulse	II clock pulse	D2	D2	D1
III clock pulse	III clock pulse	D3	D3	D2	D1
IV clock pulse	IV clock pulse	D4	D4	D3	D2	D1

For example, in case of writing 1011 combination in the register, the truth table has the following view:

CLK1	CLK2	D	Q0	Q1	Q2	Q3
		X
I clock pulse	I clock pulse
II clock pulse	II clock pulse
III clock pulse	III clock pulse
IV clock pulse	IV clock pulse

Bulks of NMOS transistors are connected to VSS

Bulks of PMOS transistors are connected to VDD

Fig. 13.2. Dynamic D trigger’s symbol and electrical circuit

CLK1 and CLK2 clock signals can be obtained from impulse generators not overlapping each other (Fig. 13.3) using the circuits of the inverter and NAND cell shown in Fig. 13.4 (Fig. 13.4).

Fig. 13.3. Logic circuit of impulse generators not overlapping each other

     

Bulks of NMOS transistors are connected to VSS

Bulks of PMOS transistors are connected to VDD

Fig. 13.4. Inverter’s and NAND logic cell’s symbols and electrical circuits

• Get the circuit netlist of 4-bit dynamic shift register (dshrg4.netl file) and put it in the following link:

/student_lab/digital_ic/variant_val/...

• Get the circuit netlist of impulse generators not overlapping each other (nonov.netl file) and put it in the following link:

/student_lab/digital_ic/variant_val/...

• Input files necessary for simulation.

For input files take:

• Input slope 50 ps
• Output capacitive load value C­=5 fF

Before writing 1011 code, it is necessary to write 0000 code in the register (register’s 0 reset).

2.1.1. The input file for measuring the delays for 4-state dynamic shift register in transition mode by using HSPICE circuit simulation tool is listed below:

*DSHRG4

*Propagation Delay

* HSPICE Netlist

.options POST=1 parhier=local

* Models section

* Include models

.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters

.param vdd = VDD_val

.param tr=TR_val

.param freq=FREQ_val

.param per=’1/freq’

.param tst=’0.5*per’

.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/dshrg4.netl'

.include '/student_lab/digital_ic/variant_val/nonov.netl.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'

***Input Signals

vclk clk 0 pulse 0 vdd 'tst' tr tr '0.5*per-tr' 'per'

vd d 0 pwl 0 0 'tst+3.75*per' 0 'tst+3.75*per+tr' vdd + 'tst+4.75*per' vdd 'tst+4.75*per+tr' 0 'tst+5.75*per' 0 'tst+5.75*per+tr' vdd

cloadq0 q0 0 LOAD_val

cloadq1 q1 0 LOAD_val

cloadq2 q2 0 LOAD_val

cloadq3 q3 0 LOAD_val

* Analysis section

* Transient Analyses

.tran ‘0.01*tr’ ‘9*per’

.probe v(*)

*Options

.option post probe

.option autostop

***Measures

***Propagation Delay

.meas tran tplh_clk_q0 trig v(clk) val='0.5*vdd' rise=5 targ v(q0) val='0.5*vdd' td='tst+3.5*per' rise=1

.meas tran tphl_clk_q0 trig v(clk) val='0.5*vdd' rise=6 targ v(q0) val='0.5*vdd' td='tst+3.5*per' fall=1

.meas tran tplh_clk_q1 trig v(clk) val='0.5*vdd' rise=6 targ v(q1) val='0.5*vdd' td='tst+3.5*per' rise=1

.meas tran tphl_clk_q1 trig v(clk) val='0.5*vdd' rise=7 targ v(q1) val='0.5*vdd' td='tst+3.5*per' fall=1

.meas tran tplh_clk_q2 trig v(clk) val='0.5*vdd' rise=7 targ v(q2) val='0.5*vdd' td='tst+3.5*per' rise=1

.meas tran tphl_clk_q2 trig v(clk) val='0.5*vdd' rise=8 targ v(q2) val='0.5*vdd' td='tst+3.5*per' fall=1

.meas tran tplh_clk_q3 trig v(clk) val='0.5*vdd' rise=8 targ v(q3) val='0.5*vdd' td='tst+3.5*per' rise=1

.meas tran tphl_clk_q3 trig v(clk) val='0.5*vdd' rise=9 targ v(q3) val='0.5*vdd' td='tst+3.5*per' fall=1

.end

2.1.2. The input file for measuring the dynamic power for 4-state dynamic shift register in transition mode by using HSPICE circuit simulation tool is listed below:

*DSHRG4

*Average Current, Power

* HSPICE Netlist

.options POST=1 parhier=local

* Models section

* Include models

.include '/student_lab/digital_ic/all_models/model_val'

* Design variables section

* Define parameters

.param vdd = VDD_val

.param tr=TR_val

.param freq=FREQ_val

.param per=’1/freq’

.param tst=’0.5*per’

.temp Temp_val

* Structural netlist section

.include '/student_lab/digital_ic/variant_val/dshrg4.netl'

.include '/student_lab/digital_ic/variant_val/nonov.netl.netl'

vvss vss gnd dc=0

vvdd vdd gnd dc='vdd'

***Input Signals

vclk clk 0 pulse 0 vdd 'tst' tr tr '0.5*per-tr' 'per'

vd d 0 pwl 0 0 'tst+3.75*per' 0 'tst+3.75*per+tr' vdd + 'tst+4.75*per' vdd 'tst+4.75*per+tr' 0 'tst+5.75*per' 0 'tst+5.75*per+tr' vdd

cloadq0 q0 0 LOAD_val

cloadq1 q1 0 LOAD_val

cloadq2 q2 0 LOAD_val

cloadq3 q3 0 LOAD_val

* Analysis section

* Transient Analyses

.tran ‘0.01*tr’ ‘tst+8*per’

.probe v(*)

*Options

.option post probe

***Measures

***Propagation Delay

.meas tran avg_i_1 avg i(vvdd) from = 'tst+4*per' to = 'tst+5*per'

.meas tran avg_i_2 avg i(vvdd) from = 'tst+5*per' to = 'tst+6*per'

.meas tran avg_i_3 avg i(vvdd) from = 'tst+6*per' to = 'tst+7*per'

.meas tran avg_i_4 avg i(vvdd) from = 'tst+7*per' to = 'tst+8*per'

.meas tran avg_pow_1 param = 'abs(vdd*avg_i_1)'

.meas tran avg_pow_2 param = 'abs(vdd*avg_i_2)'

.meas tran avg_pow_3 param = 'abs(vdd*avg_i_3)'

.meas tran avg_pow_4 param = 'abs(vdd*avg_i_4)'

.end

Steps to Perform the Work

Simulation of 4-State Dynamic Shift Register

In transition mode:

1. Get input and output signal waveforms,
2. Measure t_PHL and t_PLH delays and their average values (t_P=(t_PHL+ t_PLH)/2)
3. Measure average dynamic power consumed in every clock pulse.

Processing the Results Obtained in the Laboratory Exercise

Fill in the results obtained through simulation in Table 7.

Report

The report should contain:

1. Studied circuits;

2. Texts from input files;

3. Calculated characteristics and parameters of circuits;

4. Characteristics obtained from simulation;

5. Results obtained from the lab exercise;

6. Brief summary.

Дата добавления: 2015-10-29