Five-transistor operational amplifier: dc analysis

The Design of Three-stage BJT Operation Amplifier

Variant 2

Prepared by:

Second-year student

Group IACS – 208

Yatsura Anastasiya

Kyiv – 2013

Content:

Theory about the design of three-stage BJT operation amplifier

1. Design of an operational amplifier using a CA 3096 n-p-n/p-n-p transistor array.....................................................................................................................3

1.1. Five-transistor operational amplifier: dc analysis.................................3

1.2. Five-transistor operational amplifier: ac analysis.................................5

1.3. Class B power amplifier............................................................................7

Problems and individuals data.....................................................................................10

Calculations..................................................................................................................11

Conclusions…………………………………………………………………………4

List of references...........................................................................................................5

The purpose of this project is to design a three-stage BJT operational amplifier.

I. THEORY 1. Design of an operational amplifier using a CA 3096 n-p-n/p-n-p transistor array

We will design an operational amplifier using a CA 3096 IC, which is an n-p-n/p-n-p transistor array consisting of three independent but matched, n-p-n transistors and two independent, but matched, p-n-p transistors. This is an IC in that all emitters, bases and collectors are separately accessible as shown in Fig.1.

Fig. 1 CA 3096 n-p-n/p-n-p transistor array

Five-transistor operational amplifier: dc analysis

All three sections of a typical operational amplifier can be implemented with the five transistors in a single CA 3096, as shown in Fig. 2. A single-ended output of an emitter-coupled pair, Q₁ and Q₂, is used to drive Q₄, a p-n-p common-emitter amplifier. The n- p-n/p-n-p pair, Q₃ and Q₅, represents a class В amplifier driven from the collector of Q₄. A resistor is used to provide the current I_EE. Since the typical h_FE values for the n-p-n and p-n-p transistors are 188 and 45 respectively, all base currents will be neglected. It is also assumed that for v_id = 0, v₀= 0. The quiescent currents and voltages are obtained assuming both bases are grounded.

Fig. 2 CA 3096 connected as operational amplifier

Assuming that the base of Q₁ is grounded, the current I_EE is found by writing the KVL equation around the following loop: base of Q₁, R₃, V_EE, and ground. So,

Because v_O= 0 when v_iD = 0, then V_C4 must be zero (this is input voltage to the output stage), which means that

Biasing for Q₄ is established by arranging V_C2 to be sufficiently below V_CC that V_EB4 = 0.6V. To accomplish this,

and finally

Because Q₁ and Q₂ are matched and I_B4 << I_C2,

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