Serial Communication Registers

The 8051 contains an on-chip serial port for communication with serial devices such as modems or for interfacing with other peripheral devices with a serial interface (A/D converters, RF/IR transmitters, etc). The Serial Data Buffer register (SBUF) located at address 99H holds both the transmit data and the receive data. Writing to SBUF loads data for transmission while reading SBUF returns the received data. Various modes of operation are programmable through the bit-addressable Serial port Control register (SCON), which is located at address 98H. Serial communication issues for C8051F020 are discussed in detail in Chapter 10.

Interrupt Management Registers

The 8051 has 5 interrupt sources which include 2 external interrupts, 2 timer interrupts and a serial port interrupt. Each interrupt can be individually enabled or disabled by writing a '1' or a '0' respectively into the Interrupt Enable register (IE). The bit 7 of the register is a global enable bit, which if cleared, will disable all interrupts. In addition, each interrupt source can be set to either one of the two priority levels i.e. High or Low. This is done through the Interrupt Priority register (IP), which is located at address B8H. Interrupts for C8051F020 are discussed in detail in Chapter 11.

Multiplexing Address and Data Bus

In order to save pins and accommodate other functions, the 8051 was designed with multiplexed address and data buses in mind. It reduces the separate 16 address and 8 data lines to a combined 16 lines of address and data.

The multiplexed mode operates by latching the low byte of the address using the ALE signal during the first half of each memory cycle. A 74HC373 (or equivalent) latch holds the low byte of the address stable for the duration of the memory cycle. During the second half of the memory cycle, data is read from or written to the data bus.

Chapter 2 Introduction to Silicon Labs' C8051F020

Introduction

This chapter gives an overview of the Silicon Labs C8051F020 micro­controller. On-chip peripherals like ADC and DAC, and other features like the cross-bar and the voltage reference generator are briefly introduced. While programming using a high level language, such as C, makes it less important to know the intricacies of the hardware architecture of the micro-controller, it is still beneficial to have some knowledge of the memory organization and special function registers. Thus, these are also covered in this chapter.

CIP-51

Silicon Labs' mixed-signal system chips utilize the CIP-51 microcontroller core. The CIP-51 implements the standard 8051 organization, as well as additional custom peripherals. The block diagram of the CIP-51 is shown in Figure 2.1.

The CIP-51 employs a pipelined architecture and is fully compatible with the MCS-51™ instruction set. The pipelined architecture greatly increases the instruction throughput over the 8051 architecture.

With the 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and is usually limited to a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 millions of instructions per second (MIPS). The CIP-51 has a total of 109 instructions. Table 2.1 summarizes the number of instructions that require 1 to 8 clock cycles to execute.

Silicon Labs' mixed-signal system chips utilise the CIP-51 micro­controller core, which is fully compatible with 8051 instruction sets.

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