General Purpose RAM

System Clock - Oscillator

The 8051 features an on-chip oscillator that is typically driven by a crystal connected to XTAL1 and XTAL2 with two external stabilizing capacitors. The nominal crystal frequency is 12 MHz for most ICs in the MCS-51™ family. The on-chip oscillator needn't be driven by a crystal; it can be replaced by a TTL clock source connected to XTAL1 instead.

On-Chip Memory Organization

The 8051 has a limited on-chip program (code) and data memory space. However it has the capability of expanding to a maximum of 64K external code memory and 64K external data memory when required.

Program Memory (i.e. code memory can either be the on-chip ROM or an external ROM as shown in Figure 1.4. When /EA (External Access) pin is tied to +5 volts, it allows the program to be fetched from the internal 4K (0000H-0FFFH) ROM. If /EA is connected to ground, then all program fetches are directed to external ROM. In addition /PSEN is used as the read strobe to external ROM, while it is not activated for the internal program fetches.

The Data Memory organization is shown in Figure 1.5. It depicts the internal and external Data Memory space available in 8051. Figures 1.6a arid 1.6b show more details of the internal data memory (Read/Write memory or Random Access Memory)

The Internal Data Memory space, as shown in Figure 1.5, is divided into three sections. They are referred to as the Lower 128, the Upper 128, and the SFR. In fact there are 384 physical bytes of memory space, though the Upper 128 and SFRs share the same addresses from location 80H to FFH. Appropriate instructions, using direct or indirect addressing modes, will access each memory block accordingly.

As shown in Figure 1.6a and 1.6b, the internal data memory space is divided into register banks (00H-1FH), bit-addressable RAM (20H-2FH), general purpose RAM (30H-7FH), and special function registers (80H-FFH).

In the Lower 128 bytes of RAM, 4 banks of 8 registers each are available to the user. The 8 registers are named RO through R7. By programming two bits in the Program Status Word (PSW), an appropriate register bank can be selected.

In the Special Function Register (SFR) block (Figure 1.6b) registers which have addresses ending with OH or 8H are byte- as well as bit-addressable. Some registers are not bit-addressable at all. For example, the Stack Pointer Register (SP) and Data Pointer Register (DPTR) are not bit-addressable.

General Purpose RAM

There are 80 bytes of general purpose RAM from address ЗОН to 7FH. The bottom 32 bytes from ООН to 2FH can be used as general purpose RAM too, although these locations have other specific use also.

Any location in the general purpose RAM can be accessed freely using the direct or indirect addressing modes. For example, to read the contents of internal RAM address 62H into the accumulator A, the following instruction could be used:

Дата добавления: 2015-07-10