States of Transistor

We can explain the characteristic curve by noting that, if I _C is the collector current flowing for a particular input voltage, the output voltage V ₀, or V _ce, is less than the supply voltage V _cc by the potential drop across R, which is I_CR. Thus

In general, I _c depends on the base current I _C and this is governed by the base-emitter or input voltage V_i.

Suppose V_i is very low or practically zero. Then I _c is practically zero, and the transistor is said to be 'cutoff'. From above, we can see that the output voltage v_o is then practically equal to V _cc or high. See Fig. 39.20 (ii). Conversely, suppose V i is high so that the transistor is 'saturated', that is, any further increase in base current produces no rise in I _c. The p.d. across R is then large and so the output voltage is practically zero from above. See Fig. 39.20 (ii).

Thus depending on the input voltage, the transistor can switch between two states—cutoff or saturation. The output, voltage then switches between two levels, +V_CC and practically 0. In the special type of computer circuits known as logic circuits or logic gates, the binary digits '1' and '0' can be represented by + V _cc and 0 respectively, or by 0 and + V _cc, by this switching of states. It should be noted that the transistor acts 'non-linearly', whereas it acts 'linearly' in amplifiers (p. 830).

Logic Gates

We can now discuss briefly some useful logic gates.

Figure 30.21 (i) shows the circuit for an inverter gate. It consists of a transistor in the common-emitter mode connection, with an appropriate load resistance R and base resistance r_A. Suppose the input is a '1', for example, + V _cc volt. A high base current then flows in r_A, and as explained before, the transistor becomes saturated and the output is '0'. Conversely, if the input is '0' (zero volt), the transistor is cutoff and the output is + V _cc or T. Thus the output is always the inverse or opposite of the input. This is shown in a so-called 'truth table' in Fig. 39.21 (i), which also contains the symbol for the inverter gate.

Figure 39.21 (ii) shows the circuit for a nor gate. It is similar to the circuit in Fig. 39.21 (i) except that two inputs and two base resistors, r_A and r_B, are provided. If both inputs are '0' or zero volt, the transistor is cutoff; hence the output is '1' or + V _CC volt. If either input or both inputs, A and B, are '1', then,

with appropriate vales for r_A and r_B, the transistor saturates and the output is

'0'. These results are shown in the truth table in Fig. 39.21 (ii), together with the symbol for this gate. It is called a nor gate because the output is Т if neither A nor В is '1'; in all other cases the output is '0'.

Figure 39.22 (i) shows in symbol form an or gate; it is made of a nor gate followed by an inverter gate, so that the output S₁ of the nor gate is inverted to produce a final output S₂. By writing the inputs A and В in truth table form as on p. 837, we find that S₂ is a '1' if either A or В is a T.

Figure 39.22 (ii) shows in symbol form an and gate; it consists of two in­verter gates followed by a nor gate. The truth table for S₁ S₂ and S₃ shows that the output S₃ is а '1' only if A and В are T.

Figure 39.22 (iii) shows the construction of a-NAND gate. The truth table shows that the output S₃ is '1' if A and B, individually or together, are not '1'.

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