L. Junction Field-Effect Transistors

The connection and structure of a p-n jun­ction FET, or a JFET are shown in Fig. 5.1. It is essentially, say, an n -type semiconductor wafer which has at its opposite ends a pair of terminals for connection into the output circuit of an amplifying stage. This circuit is energized from a supply voltage source E_D and contains a load resistance, R_D. The output current flowing along a JFET is con­stituted by majority carriers which are electrons. The input (control) circuit of the JFET is formed with the aid of a third electrode made to a region of an opposite type of con­duction which is a p- typeregion in our example. The input supply voltage source U_SG produces a reverse voltage across the only p-n junction of the JFET. No forward voltage isapplied to the p-n junction because the input resistance would have been very small. The signal sourceis connected in the input circuit.

Fig. 5.1. Connection of an n -channel JFET in a circuit and its graphical symbol

When the input voltage is varied, a change occurs in the reverse voltage across the p-n junction, and this varies the width of the depletion (barrier) layer bounded by the dashed lines in Fig. 5.1 b. This region is called the channel.

The electrode emitting majority carriers into the channel is called the source (S) and the electrode collecting them is called the drain (D). The control elec­trode intended to vary the cross-sectional area of the conducting channel is called the gate (G).

As the reverse gate voltage U_SG is increased, so does the width of the depletion layer in the p-n junction, but the cross-sectional area of theconducting channel is reduced. In consequence, its d.c. resistance R_C increases and the drain current I_D decreases. At some value of the source-to-gate voltage, called the pinch-off voltage U_P the cross-sec­tional area of the channel reduces to zero and I_D falls to an extremely small value. As a result, the JFET is turned off. Conversely, at U_SG equal to zero, the channel has a maximum cross-sec­tional area, R_C is a minimum and I_D is a maximum. In the circumstances the pinch-off voltage will be se­veral volts.

The control action of the gate is illustrated by the transfer,or drain-to-gate, characteristics, I_D (U_SG) with U_DS held constant (Fig. 5.2).

Fig. 5.2. Transfer characteristics of an n -channel JFET

As is seen from Fig. 5.3, the output (or drain) characteristics of a JFET relate the drain cur­rent, I_D, to the drain-to-source voltage, U_DS, that is, I_D (U_DS) with U_SG held constant. They show that with an increase in U_DS at first I_D rises at a fairly high rate, then its rise slows down, and finally ceases completely - the device reaches a state not unlike saturation. The point is that a rise in U_DS should have caused the drain current to rise as well, but since the reverse voltage across p-n junction also rises, the depletion layer widens, the channel's width is decreased and I_D is forced to fall.

Fig. 5.3. Output characteristics of an n -channel JFET

When a high negative voltage is applied to the gate, I_D is reduced, and the characteristic is shifted downwards.

As a rule, JFETs are operated within the quietly sloping portion of their characteristics, that is, within the region which is called, somewhat misleadingly, the saturation region. The pinch-off voltage is called the cutoff voltage. It is to be noted that p -channel JFETs use supply voltages whose polarities are opposite.

Several parameters are used to specify the performance of JFETs. The most important one is the transconductance. It is given by:

g_m = ∆I_d /∆U_SG with U_DS = const (5.1)

and may take on values up to several milliamperes per volt (mS).

For example, g_m = 3 mA/V indicates that a change of 1 V in gate voltage will produce a change of 3 mA in drain current.

The second most important parameter is the output conductance g₂₂ as measured between its drain and source. It is given by:

g₂₂ = ∆I_d /∆U_DS with U_GS = const. (5.2)

Within the saturation region of the output characteristics g₂₂ may be several tens microsiemens.

A third parameter, called the voltage gain μ, is used:

μ = - ∆U_d /∆U_SG =- g_m / g₂₂ with I_D = const. (5.3)

Within the saturation region of the output characteristics μ may run into several tens.

The input resistance of a JFET is found in the usual way:

R_in = ∆U_SG /∆I_G with U_DS = const. (5.4)

Because I_G is a reverse current for the p-n junction and is therefore very small, R_in is units or tens of megohms.

A JFET also has an input capacitance between its gate and source, C_GS, which is the junction capacitance of the p-n junction and has a value of several picofarads. The transfer capacitance (that is, one from gate to drain), C_GD, has a lower value, the smallest capacitance being that between source and drain, C_SD, or the output capacitance of a JFET.

Figure 5.1 shows the most com­monly used common-source (CS) connection which is similar to the CE configuration. A CS stage yields a high power gain and inverts the phase of voltage in the am­plification mode. The stage voltage gain may approximately be written as:

= g_m R_D. (5.5)

Figure 5.4 shows an linear equivalent circuit of a JFET with the CS connection. The equivalent constant-current generator g_mU_SG reflects the ampli­fication supplied by the JFET.

Fig. 5.4. Linear equivalent circuit of a JFET

Practical amplifying stages ordinarily use a single supply voltage source E_D , as shown in Fig. 5.5 for n -channel JFETs. In order to derive the direct reverse voltage to be applied to the gate p-n junction, the source lead contains a resistor R_S shunted by a capacitor C_S. The direct source current I_S produces across R_S a bras voltage drop:

U_SG = I_S R_S ,

which is applied via the resistor R_G = 1MΩ to the p-n junction. The value of R_S is found by the equation:

R_S = U_SG / I_S.

Fig. 5.5. JFET drawing power from a single supply

Sometimes the signal voltage supplied by the signal generator contains a direct com­ponent which ought not to reach the transistor input. To achieve this, the signal voltage is fed via a d. c. blocking capacitor C_B1.

Figure 5.6 shows an n -channel JFET con­nected in a common-gate (CG) circuit (a) and a common-drain (CD) circuit (b). The CG configu­ration does not produce current amplification, and so its power gain is a small fraction of that supplied by the CS circuit. Its input resistance is low because the input current is the sourse current. When used as an amplifier, this scheme does not invert the phase of output voltage.

Fig. 5.6. JFET connected in (a) the common-gate (CG) con­figuration and (b) the common-drain (CD) confi­guration

A CD stage (Fig. 5.6b) may be called a source follower. The stage voltage gain is unity very nearly. The output voltage follows the input voltage in both phase and magnitude. This configuration has a relatively low output re­sistance and an increased input resistance.

In addition to a high input resistance, JFETs have a number of other advantages over bipolar transistors. Because I_D in JFETs is due to the motion of majority carriers whose concentra­tion is mainly governed by the impurity concen­tration and therefore is only slightly dependent on temperature, JFETs are less sensitive to temperature variations.

JFETs are fabricated from silicon because the gate current, which is the reverse current for the p-n junction, is then only a small fraction of its value for germanium. At 20°C, the reverse d.c. gate current may be as low as 1 nA.

Дата добавления: 2015-11-14