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entity compodff is -- --define prime project compodff
port(RSn: in bit;
CLK: in bit;
D:in bit;
Q: out bit);
end compodff;
architecture dffco of compodff is
begin
process(RSn, CLK)
begin
if(RSn = '0') then
Q <= '0';
elsif(CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
end dffco;
entity composiftdff is
port(RSn: in bit;
CLK: in bit;
SI: in bit;
SO: out bit);
end composiftdff;
architecture shift of composiftdff is
component compodff
port (RSn: in bit;
CLK: in bit;
D: in bit;
Q: out bit);
end component;
signal T: bit_vector(6 downto 0);
begin
bit7: compodff port map (RSn=>RSn, CLK=>CLK, D=>SI, Q=>T(6));
bit6: compodff port map (RSn, CLK, T(6), T(5));
bit5: compodff port map (RSn, CLK, T(5), T(4));
bit4: compodff port map (RSn=>RSn, CLK=>CLK, D=>T(4), Q=>T(3));
bit3: compodff port map (RSn, CLK, T(3), T(2));
bit2: compodff port map (RSn, CLK, T(2), T(1));
bit1: compodff port map (RSn, CLK, T(2), T(0));
bit0: compodff port map (RSn, CLK, T(0), SO);
end shift;
Project D_FF
---------------------------------------------------------------
Entity D_FF is
port (D_in: in bit;
CLK: in bit;
Q_out: out bit);
End D_FF;
Architecture D_FF_a of D_FF is
Component INV_e
port (X: in bit;
Y: out bit);
End component;
Component DL_e
port(D, C: in bit;
Q: out bit);
End component;
signal q_t, inv_t, inv_t1: bit;
Begin
U1: INV_e port map(CLK, inv_t);
U2: INV_e port map(inv_t, inv_t1);
U3: DL_e port map(D => D_in, C => inv_t, Q => q_t);
U4: DL_e port map(D => q_t, C => inv_t1, Q => Q_out);
End D_FF_a;
--------------------
entity DL_e is
port(D, C: in bit;
Q: out bit);
end DL_e;
architecture DL_a of DL_e is
begin
U1: process(C)
begin
if C = '1' then Q <= D;
end if;
end process;
end DL_a;
-------------------
entity INV_e is
port (X: in bit;
Y: out bit);
end INV_e;
architecture INV_a of INV_e is
begin
Y <= not X;
end INV_a;
-----------------------------------------------------------
Project Reg4_co
-----------------------------------------------------------
Entity Reg4_co is
port(RedD: in bit_vector (3 downto 0);
clk,rst: in bit;
RegQ: out bit_vector (3 downto 0));
End Reg4_co;
Architecture Red4_co_arch of Reg4_co is
Component DFF_RST is
port(D, clk, rst: in bit;
Q: out bit);
End component;
Begin
bit0: component DFF_RST
port map(D=>RedD(0),clk=>clk,rst=>rst, Q=>RegQ(0));
bit1: component DFF_RST
port map (D=>RedD(1), clk=>clk, rst=>rst, Q=>RegQ(1));
bit2: component DFF_RST
port map (D=>RedD(2), clk=>clk, rst=>rst, Q=>RegQ(2));
bit3: component DFF_RST
port map (D=>RedD(3), clk=>clk, rst=>rst, Q=>RegQ(3));
End Red4_co_arch;
entity DFF_RST is
port(D, clk, rst: in bit;
Q: out bit);
end DFF_RST;
architecture DFF_RST_arch of DFF_RST is
begin
process(rst, clk)
begin
if rst = '1' then Q <= '0';
else
if clk'event and clk = '1' then
Q <= D;
end if;
end if;
end process;
end DFF_RST_arch;
-------------------------------------------------------------
Project adder_2
-------------------------------------------------------------
Entity adder_2 is
port(a21,b21,a12,b12: in bit;
c22, s12, s22:out bit);
End adder_2;
Architecture strucr_ad2 of adder_2 is
component add1 port (b1,b2: in bit;
c1,s1: out bit);
End component;
component add2 port (c1,a1,a2: in bit;
c2,s2: out bit);
End component;
signal c1: bit;
Begin
circ1: add1 port map(b12, a12,c1,s12);
circ2: add2 port map(c1,b21,a21,c22,s22);
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