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-- 4-bit Binary Down Counter with clock enable
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DE is
port(CLK, CE: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DE;
architecture v1 of CNTB4DE is
signal count_I: unsigned (3 downto 0);
begin
process(CLK, count_i)
begin
if (CLK = '1' and CLK'event) then
if CE = '1' then
count_i <= count_i - "1";
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
-- 4-bit Loadable Binary Down Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DL is
port(CLK, LD: in std_logic;
D3, D2, D1, D0: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DL;
architecture v1 of CNTB4DL is
signal data, data_i, count_i: unsigned (3 downto 0);
begin
data <= D3 & D2 & D1 & D0;
data_i <= unsigned(data);
process(CLK, LD, data_i, count_i)
begin
if (CLK = '1' and CLK'event) then
if (LD='1') then
count_i <= data_i;
else
count_i <= count_I - "1";
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
-- 4-bit Loadable Binary Down Counter with clock enable
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DLE is
port(CLK, CE, LD: in std_logic;
D3,D2,D1,D0: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DLE;
architecture v1 of CNTB4DLE is
signal data, data_i, count_i: unsigned (3 downto 0);
begin
data <= D3 & D2 & D1 & D0;
data_i <= unsigned(data);
process(CLK, LD, data_i, count_i)
begin
if (CLK = '1' and CLK'event) then
if CE = '1' then
if (LD='1') then
count_i <= data_i;
else
count_i <= count_i - "1";
end if;
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
-- 4-bit Loadable Binary Down Counter with asynchronous reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DLR is
port(CLK, RST, LD: in std_logic;
D3, D2, D1, D0: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DLR;
architecture v1 of CNTB4DLR is
signal data, data_i, count_i: unsigned(3 downto 0);
begin
data <= D3 & D2 & D1 & D0;
data_i <= unsigned(data);
process(CLK, RST, LD, data_i, count_i)
begin
if (RST='1') then
count_i <= x"0";
elsif (CLK = '1' and CLK'event) then
if (LD='1') then
count_i <= data_i;
else
count_i <= count_i - "1";
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
-- 4-bit Loadable Binary Down Counter with asynchronous reset -- and clock enable
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DLRE is
port(CLK, CE, RST, LD: in std_logic;
D3, D2, D1, D0: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DLRE;
architecture v1 of CNTB4DLRE is
signal data,data_i,count_i: unsigned (3 downto 0);
begin
data <= D3 & D2 & D1 & D0;
data_i <= unsigned(data);
process(CLK,RST,LD,data_i,count_i)
begin
if (RST='1') then
count_i <= x"0";
elsif (CLK = '1' and CLK'event) then
if CE = '1' then
if (LD='1') then
count_i <= data_i;
else
count_i <= count_i - "1";
end if;
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
-- 4-bit Loadable Binary Down Counter with asynchronous set
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity CNTB4DLS is
port(CLK, PRE, LD: in std_logic;
D3, D2, D1, D0: in std_logic;
Q3, Q2, Q1, Q0: out std_logic);
end CNTB4DLS;
architecture v1 of CNTB4DLS is
signal data, data_i, count_i: unsigned (3 downto 0);
begin
data <= D3 & D2 & D1 & D0;
data_i <= unsigned(data);
process(CLK, PRE, LD, data_i, count_i)
begin
if (PRE='1') then
count_i <= x"F";
elsif (CLK = '1' and CLK'event) then
if (LD='1') then
count_i <= data_i;
else
count_i <= count_i - "1";
end if;
end if;
end process;
Q3 <= count_i(3) after 1 ns;
Q2 <= count_i(2) after 1 ns;
Q1 <= count_i(1) after 1 ns;
Q0 <= count_i(0) after 1 ns;
end v1;
Integer Counter Universal MultiOut
ENTITY counters IS
PORT
(
d: IN INTEGER RANGE 0 TO 255;
clk: IN BIT;
clear: IN BIT;
ld: IN BIT;
enable: IN BIT;
up_down: IN BIT;
qa: OUT INTEGER RANGE 0 TO 255;
qb: OUT INTEGER RANGE 0 TO 255;
qc: OUT INTEGER RANGE 0 TO 255;
qd: OUT INTEGER RANGE 0 TO 255;
qe: OUT INTEGER RANGE 0 TO 255;
qf: OUT INTEGER RANGE 0 TO 255;
qg: OUT INTEGER RANGE 0 TO 255;
qh: OUT INTEGER RANGE 0 TO 255;
qi: OUT INTEGER RANGE 0 TO 255;
qj: OUT INTEGER RANGE 0 TO 255;
qk: OUT INTEGER RANGE 0 TO 255;
ql: OUT INTEGER RANGE 0 TO 255;
qm: OUT INTEGER RANGE 0 TO 255;
qn: OUT INTEGER RANGE 0 TO 255
);
END counters;
ARCHITECTURE a OF counters IS
BEGIN
-- An enable counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt:= cnt + 1;
END IF;
END IF;
qa <= cnt;
END PROCESS;
-- A synchronous load counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt:= d;
ELSE
cnt:= cnt + 1;
END IF;
END IF;
qb <= cnt;
END PROCESS;
-- A synchronous clear counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
cnt:= cnt + 1;
END IF;
END IF;
qc <= cnt;
END PROCESS;
-- An up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
cnt:= cnt + direction;
END IF;
qd <= cnt;
END PROCESS;
-- A synchronous load enable counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt:= d;
ELSE
IF enable = '1' THEN
cnt:= cnt + 1;
END IF;
END IF;
END IF;
qe <= cnt;
END PROCESS;
-- An enable up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt:= cnt + direction;
END IF;
END IF;
qf <= cnt;
END PROCESS;
-- A synchronous clear enable counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
IF enable = '1' THEN
cnt:= cnt + 1;
END IF;
END IF;
END IF;
qg <= cnt;
END PROCESS;
-- A synchronous load clear counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
IF ld = '0' THEN
cnt:= d;
ELSE
cnt:= cnt + 1;
END IF;
END IF;
END IF;
qh <= cnt;
END PROCESS;
-- A synchronous load up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt:= d;
ELSE
cnt:= cnt + direction;
END IF;
END IF;
qi <= cnt;
END PROCESS;
-- A synchronous load enable up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt:= d;
ELSE
IF enable = '1' THEN
cnt:= cnt + direction;
END IF;
END IF;
END IF;
qj <= cnt;
END PROCESS;
-- A synchronous clear load enable counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
IF ld = '0' THEN
cnt:= d;
ELSE
IF enable = '1' THEN
cnt:= cnt + 1;
END IF;
END IF;
END IF;
END IF;
qk <= cnt;
END PROCESS;
-- A synchronous clear up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
cnt:= cnt + direction;
END IF;
END IF;
ql <= cnt;
END PROCESS;
-- A synchronous clear enable up/down counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
VARIABLE direction: INTEGER;
BEGIN
IF (up_down = '1') THEN
direction:= 1;
ELSE
direction:= -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt:= 0;
ELSE
IF enable = '1' THEN
cnt:= cnt + direction;
END IF;
END IF;
END IF;
qm <= cnt;
END PROCESS;
-- A modulus 200 up counter
PROCESS (clk)
VARIABLE cnt: INTEGER RANGE 0 TO 255;
CONSTANT modulus: INTEGER:= 200;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF cnt = modulus THEN
cnt:= 0;
ELSE
cnt:= cnt + 1;
END IF;
END IF;
qn <= cnt;
END PROCESS;
END a;
Binary Counter Kurs Project
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity CNT_4B is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
ENABLE: in STD_LOGIC;
FULL: out STD_LOGIC;
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end CNT_4B;
architecture CNT_4B of CNT_4B is
signal Qint: STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK, RESET)
begin
if RESET = '1' then
Qint <= (others => '0');
elsif CLK='1' and CLK'event then
if ENABLE = '1' then
if Qint = 9 then
Qint <= (others => '0');
else
Qint <= Qint + 1;
end if;
end if;
end if;
end process;
Q <= Qint;
FULL <= '1' when (Qint = 9) else '0';
end CNT_4B;
BinaryRombi_Reg Kurs Project
ENTITY combi_reg IS
PORT
(
enable, clk, clr, pre, load: IN BIT;
data: IN BIT_vector(3 downto 0);
Q: out BIT_vector(3 downto 0));
END combi_reg;
ARCHITECTURE maxpld OF combi_reg IS
signal q1, q3, q5, q6: BIT_vector(3 downto 0);
BEGIN
PROCESS (enable)
BEGIN
IF enable = '0' THEN
q1 <= (others=>'0');
end if;
END PROCESS;
-- Register with active-high Clock & asynchronous Clear
PROCESS (clk, clr)
BEGIN
IF clr = '1' THEN
q3 <= (others=>'0');
ELSIF clk'EVENT AND clk = '1' THEN
q3 <= data;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous Preset
PROCESS (clk, pre)
BEGIN
IF pre = '1' THEN
q5 <= x"F";
ELSIF clk'EVENT AND clk = '1' THEN
q5 <= data;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous load
PROCESS (clk, load, data)
BEGIN
IF load = '1' THEN
q6 <= data;
ELSIF clk'EVENT AND clk = '1' THEN
q6 <= data;
END IF;
END PROCESS;
Q <= q3 when clr = '1' else
q5 when pre = '1' else
q6 when load = '1' else
q1 when enable = '0' else data;
END maxpld;
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