Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type

Bit	Description	Read	Write	Value after Reset
6:0	Configuration Layout Type.Specifies layout of registers 10h through 3Fh in configuration space. Header Type 0 is defined for all PCI devices other than PCI-to-PCI bridges (Header Type 1) and Cardbus bridges (Header Type 2).	Yes	No	0h
	Multi-Function Device.Value of 1 indicates multiple (up to eight) functions (logical devices) each containing its own, individually addressable configuration space, 64 Lwords in size. Note: Hardwired to 0 (that is, device is single function, as multi-function = false).	Yes	No

Register 10-9. (PCIBISTR; PCI:0Fh) PCI Built-In Self Test (BIST)

Bit	Description	Read	Write	Value after Reset
7:0	Built-In Self Test.Value of 0 indicates device passed its test. Not Supported.	Yes	No	0h

Register 10-10. (PCIBAR0; PCI:10h) PCI Base Address 0 for Memory Accesses to Local Configuration Registers

Bit	Description	Read	Write	Value after Reset
	Memory Space Indicator.Writing 0 indicates the register maps into Memory space. Writing 1 indicates the register maps into I/O space. Note: Hardwired to 0.	Yes	No
2:1	Register Location.Values: 00 = Locate anywhere in 32-bit Memory Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit Memory Address space 11 = Reserved Note: Hardwired to 00.	Yes	No
	Prefetchable.Writing 1 indicates there are no side effects on reads. Does not affect PCI 9030 operation. Note: Hardwired to 0.	Yes	No
6:4	Memory Base Address.Memory base address for access to Local Configuration registers (requires 128 bytes). Note: Hardwired to 000.	Yes	No
31:7	Memory Base Address.Memory base address for access to Local Configuration registers.	Yes	Yes	0h

Note: PCIBAR0 can be enabled or disabled by using CNTRL[13:12].

Дата добавления: 2015-07-10