Register 10-27. (PMC; PCI:42h) Power Management Capabilities

Bit	Description	Read	Write	Value after Reset
2:0	Version.The value 001 indicates compliance with PCI Bus Power Management Interface Specification, Revision 1.0, and its definition for PMC register format. This value can be changed in serial EEPROM to 010 to indicate compliance with PCI Power Mgmt. r1.1. (Refer to PCI 9030 Design Note #1 for PMC register definition under PCI Power Mgmt. r1.1.)	Yes	Serial EEPROM
	PCI Clock Required for PME# Signal.When set to 1, indicates a function relies on PCI clock presence for PME# operation. The PCI 9030 does not require the PCI clock for PME#, so this bit should be set to 0 in serial EEPROM.	Yes	Serial EEPROM
	Auxiliary Power Source.Because the PCI 9030 does not support PME# while in a D3cold state, this bit is always set to 0. Not Supported.	Yes	No
	Device-Specific Initialization (DSI).When set to 1, the PCI 9030 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it.	Yes	Serial EEPROM
8:6	Reserved.	Yes	No
	D1_Support.When set to 1, the PCI 9030 supports the D1power state. Not Supported.	Yes	No
	D2_Support.When set to 1, the PCI 9030 supports the D2power state. Not Supported.	Yes	No
15:11	PME_Support.Indicates power states in which the PCI 9030 may assert PME#. Values: XXXX1 = PME# can be asserted from D0 XXXXX = The PCI 9030 does not support the D1 power state XXXXX = The PCI 9030 does not support the D2 power state X1XXX = PME# can be asserted from D3hot XXXXX = PME# cannot be asserted from D3cold	Yes	[14:11]: Serial EEPROM   [15]: No

Register 10-28. (PMCSR; PCI:44h) Power Management Control/Status

Bit	Description	Read	Write	Value after Reset
1:0	Power State.Determines or changes the current power state. Values: 00 = D0 11 = D3hot Transition from a D3hotstate to a D0 state causes a soft reset, LRESETo# assertion, an LPMINT# pulse, clearing of Local Configuration registers (including the Chip Select and Control registers), and reloading of the Configuration registers from the serial EEPROM. In a D3hotstate, PCI Memory and I/O accesses are disabled, as well as PCI interrupts, and only configuration is allowed.	Yes	Yes
7:2	Reserved.	Yes	No	0h
	PME_En.Writing 1 enables PME# to be asserted.	Yes	Yes/ Serial EEPROM
12:9	Data_Select.Selects which data to report through the Data register and Data_Scale bits.	Yes	Yes/ Serial EEPROM	0h
14:13	Data_Scale.Indicates the scaling factor to use when interpreting the Data register value. Value and meaning of this bit depends on the data value selected by the Data_Select bit. When the Local CPU initializes the Data_Scale values, it must use the Data_Select bit to determine which Data_Scale value it is writing. For Power Consumed and Power Dissipated data, the following scale factors are used. Unit values are in watts. Values: 0 = Unknown 1 = 0.1x 2 = 0.01x 3 = 0.001x Note: Information regarding hidden register use is provided in Section 7.2.1.	Yes	Serial EEPROM by way of PMDATASCALE
	PME_Status.Indicates PME# is being driven if the PME_En bit is set (PMCSR[8]=1). Asserting LPMESET input high sets this bit; writing 1 from the PCI Bus clears this bit to 0. Depending on the current power state, set only if the appropriate PME_Support bit(s) is set (for example, PMC[15:11]=1).	Yes	Local Interrupt/Set, PCI/Clr

Дата добавления: 2015-07-10