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Register 10-2. (PCICR; PCI:04h) PCI Command

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Bit Description Read Write Value after Reset
  I/O Space.Writing 1 allows the device to respond to I/O Space accesses. Writing 0 disables the device from responding to I/O Space accesses. Yes Yes  
  Memory Space.Writing 1 allows the device to respond to Memory Space accesses. Writing 0 disables the device from responding to Memory Space accesses.   Yes   Yes  
  Master Enable. Not Supported. Yes No  
  Special Cycle. Not Supported. Yes No  
  Memory Write and Invalidate Enable. Not Supported. Yes No  
  VGA Palette Snoop. Not Supported. Yes No  
  Parity Error Response.Writing 0 indicates parity error is ignored and the operation continues. Writing 1 indicates parity checking is enabled. Yes Yes  
    Stepping Control.Controls whether a device does address/data stepping. Writing 0 indicates the device never does stepping. Writing 1 indicates the device always does stepping. Note: Hardwired to 0.     Yes     No    
  SERR# Enable.Writing 1 enables SERR# driver. Writing 0 disables SERR# driver. Yes Yes  
    Fast Back-to-Back Enable.Indicates what type of fast back-to-back transfers a Master can perform on the bus. Writing 1 indicates fast back-to-back transfers can occur to any agent on the bus. Writing 0 indicates fast back-to- back transfers can occur only to the same agent as in the previous cycle. Note: Hardwired to 0.     Yes     No    
15:10 Reserved. Yes No 0h


 

 

Register 10-3. (PCISR; PCI:06h) PCI Status

 

Bit Description Read Write Value after Reset
3:0 Reserved. Yes No 0h
    New Capability Functions Support.Writing 1 supports New Capabilities Functions. If enabled, the first New Capability Function ID is located at the PCI Configuration Space offset determined by the New Capabilities linked list pointer value at offset 34h. Can be written only from the serial EEPROM. Read-only from the PCI Bus.     Yes   Serial EEPROM    
6:5 Reserved. Yes No  
  Fast Back-to-Back Capable.Writing 1 indicates an adapter can accept fast back-to-back transactions. Note: Hardwired to 1.   Yes   No  
  Master Data Parity Error. Not Supported. Yes No  
  10:9 DEVSEL# Timing.Indicates timing for DEVSEL# assertion. Writing 01 sets this bit to medium. Note: Hardwired to 01.   Yes   No  
  Signaled Target Abort.When set to 1, indicates the PCI 9030 signaled a Target Abort. Writing 1 clears this bit to 0. Yes Yes/Clr  
  Received Target Abort.When set to 1, indicates the PCI 9030 received a Target Abort signal. Not Supported. Yes No  
  Received Master Abort.When set to 1, indicates the PCI 9030 received a Master Abort signal. Not Supported. Yes No  
  Signaled System Error.When set to 1, indicates the PCI 9030 reported a system error on SERR#. Writing 1 clears this bit to 0. Yes Yes/Clr  
  Detected Parity Error.When set to 1, indicates the PCI 9030 detected a PCI Bus parity error, even if parity error handling is disabled [the Parity Error Response bit in the Command register is clear (PCICR[6]=0]. This bit is set when the PCI 9030 detects a parity error during a PCI Address phase or a PCI Data phase when it is the Target of a write. Writing 1 clears this bit to 0.   Yes   Yes/Clr  

 

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Читайте в этой же книге: Timing Diagram 4-25. PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetch Counter Set to 8, Multiplexed Mode Only | Timing Diagram 4-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus), Non-Multiplexed Mode Only | Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only | Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only | Chip Select Timing Diagrams Local Chip Selects | Figure 6-1. Interrupt and Error Sources | Timing Diagram 6-3. GPIO[8:0] as Outputs | System Changes Power Mode Example PCI Power Management | Controlling Connection Processes CompactPCI Hot Swap | Figure 9-1. VPD Capabilities |
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Table 10-2. PCI Configuration Register Address Mapping| Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type
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