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Bit | Description | Read | Write | Value after Reset |
7:0 | New Capability Pointer.Provides an offset into PCI Configuration Space for location of the first item in the New Capabilities Linked List. Bits [1:0] are reserved by PCI r2.2, and should be set to 00 (the byte value points to an Lword boundary.) Note: These bits must always contain the default value 40h. (Refer to PCI 9030 Errata #9.) | Yes | Serial EEPROM | 40h |
31:8 | Reserved. | Yes | No | 0h |
Register 10-21. (PCIILR; PCI:3Ch) PCI Interrupt Line
Bit | Description | Read | Write | Value after Reset |
7:0 | Interrupt Line Routing Value.Indicates to which system interrupt controller(s) input the interrupt line is connected. The PCI 9030 does not use this value, rather the value is used by device drivers and operating systems for priority and vector information. Values in this register are system-architecture specific. For x86-based PCs, the values in this register correspond to IRQ numbers (0 through 15) of the standard dual 8259 interrupt controller configuration. The value 255 is defined as “unknown” or “no connection” to the interrupt controller. Values 15 through 255 are reserved. | Yes | Yes | 0h |
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Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1 | | | Register 10-27. (PMC; PCI:42h) Power Management Capabilities |