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Register 10-13. (PCIBAR3; PCI:1Ch) PCI Base Address 3 for Accesses to Local Address Space 1

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Bit Description Read Write Value after Reset
  Memory Space Indicator.Writing 0 indicates the register maps into Memory space. Writing 1 indicates the register maps into I/O space. (Specified in the LAS1RR register.)   Yes   No  
    2:1 Register Location.Values: 00 = Locate anywhere in 32-bit Memory Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit Memory Address space 11 = Reserved (Specified in the LAS1RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.     Yes     Mem: No I/O: Bit 1 No, Bit 2 Yes    
  Prefetchable (If Memory Space).Writing 1 indicates there are no side effects on reads. Reflects value of LAS1RR[3] and provides only status to the system. Does not affect PCI 9030 operation. The associated Bus Region Descriptor register (LAS1BRD) controls prefetching functions of this address space. (Specified in the LAS1RR register.) If I/O Space, bit 3 is included in base address.   Yes     Mem: No I/O: Yes  
31:4 Memory Base Address.Memory base address for access to Local Address Space 1. Yes Yes 0h

Note: If allocated, Local Address Space 1 can be enabled or disabled by setting or clearing LAS1BA[0].



 

 

Register 10-14. (PCIBAR4; PCI:20h) PCI Base Address 4 for Accesses to Local Address Space 2

 

Bit Description Read Write Value after Reset
  Memory Space Indicator.Writing 0 indicates the register maps into Memory space. Writing 1 indicates the register maps into I/O space. (Specified in the LAS2RR register.)   Yes   No  
    2:1 Register Location.Values: 00 = Locate anywhere in 32-bit Memory Address space 01 = PCI r2.1, Locate below 1-MB Memory Address space PCI r2.2, Reserved 10 = Locate anywhere in 64-bit Memory Address space 11 = Reserved (Specified in the LAS2RR register.) If I/O Space, bit 1 is always 0 and bit 2 is included in the base address.     Yes     Mem: No I/O: Bit 1 No, Bit 2 Yes    
  Prefetchable (If Memory Space).Writing 1 indicates there are no side effects on reads. Reflects value of LAS2RR[3] and provides only status to the system. Does not affect PCI 9030 operation. The associated Bus Region Descriptor register (LAS2BRD) controls prefetching functions of this address space. (Specified in the LAS2RR register.) If I/O Space, bit 3 is included in base address.   Yes     Mem: No I/O: Yes  
31:4 Memory Base Address.Memory base address for access to Local Address Space 2. Yes Yes 0h

Note: If allocated, Local Address Space 2 can be enabled or disabled by setting or clearing LAS2BA[0].

 

 

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Читайте в этой же книге: Timing Diagram 4-37. PCI r2.2 Features Enable, Non-Multiplexed Mode Only | Timing Diagram 4-39. Locked PCI Target Read Followed by Write and Release (LLOCKo#), Non-Multiplexed Mode Only | Chip Select Timing Diagrams Local Chip Selects | Figure 6-1. Interrupt and Error Sources | Timing Diagram 6-3. GPIO[8:0] as Outputs | System Changes Power Mode Example PCI Power Management | Controlling Connection Processes CompactPCI Hot Swap | Figure 9-1. VPD Capabilities | Table 10-2. PCI Configuration Register Address Mapping | Register 10-2. (PCICR; PCI:04h) PCI Command |
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Register 10-8. (PCIHTR; PCI:0Eh) PCI Header Type| Register 10-20. (CAP_PTR; PCI:34h) New Capability Pointer
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