Programmable

bursts 1-1, 1-3

chip select 1-2, 5-1–5-2

FIFOs, zero wait state burst 1-3 internal registers 3-1, 4-1

Prefetch Counter 1-5

wait state generator 11-12, 11-14, 11-15

wait states 1-3, 1-5

Programming Interface 0 1-2, 8-1, 8-4, 10-14

PROT_AREA 3-4, 9-2, 10-33

pull-up/pull-down resistors 8-1, 11-1–11-3

PVPD_NEXT 3-3, 3-7, 9-1, 10-15

PVPDAD 9-1, 10-15

PVPDATA 9-1, 10-15

PVPDCNTL 3-3, 9-1, 10-15

R

ranges, operating 12-1, 12-2

RD# 2-4, 10-22–10-30, 11-14, 11-17, 13-3, 13-6

read 2-1

accesses 2-10, 3-7, 4-4

FIFOs 1-3, 1-5, 2-10, 4-4

Local Bus accesses 2-10

PCI Configuration timing diagram 3-9, 4-14

PCI initialization 4-5

PCI Memory timing diagrams 3-10, 4-15 PCI Power mode example 7-3

PCI r2.2 Features Enable 4-42

PCI Target 1-3, 1-5, 3-1, 4-1, 4-2, 4-3, 4-4, 4-8, 10-35

programmable strobe timing on local bus 1-1 random read and write 9-2

registers 10-4–10-37 sequential read only 9-1

serial EEPROM 1-5, 3-1–3-2, 9-2

timing diagrams See timing diagrams 4-33 VPD 9-1–9-2

write PCI power management 7-1

Read Ahead mode, PCI Target 1-1, 3-1, 4-3, 10-35 Prefetch mode, in addition to 4-1

read accesses 2-10

supported by PCI 9030 1-3

timing diagram 4-43

read strobe delay 1-1, 2-6, 10-22–10-30, 11-14, 11-17

READY# 2-5, 2-8, 11-2, 11-14, 11-17, 13-3, 13-6

expansion ROM bus region descriptor register 10-29 input 2-10, 10-21, 10-23, 10-25, 10-27

product ordering and support

to registers

timeout logic, SMARTarget 1-1 timing diagram 4-34

wait states 4-1

Дата добавления: 2015-07-10