The flexibility attainable through microprogramming makes it possible to design the data path section of a processor, that is, the ALU, registers, and internal connections, independently of its

Bit Slices

The flexibility attainable through microprogramming makes it possible to design the data path section of a processor, that is, the ALU, registers, and internal connections, independently of its instruction set. Moreover, it is possible to design general-purpose microinstruction sequencing hardware that can be used in conjunction with a wide range of data path configurations and instruction sets. In other words, we can define building blocks, which can be easily assembled into a computer that meets the needs of a given application. The capabilities and the instruction set of such a computer are determined by the particular building blocks chosen, by the way they are interconnected, and of course by the microprogram.

The flexibility of this building block approach can be enhanced considerably if the blocks can be used to build processors of arbitrary word length. This is the basis of the bit-slice idea. A bit slice is a "slice" through the data path of a typical processor. It contains all circuits necessary to provide ALU functions, register transfers, and control functions for a few bits only, typically 2, 4, or 8. The connection patterns for the circuits on the slice are under microprogram control. The necessary control signals are provided by other building blocks.

A 4-bit slice provides the functions of an ALU and a number of registers for 4 bits of data. It also provides the signals necessary for interconnection of a number of such slices side by side to form a wider data path. Thus, it is possible to use four slices to form the basis of a 16-bit processor, or eight slices for a 32-bit processor.

The bit-slice building block is highly compatible with VLSI technology. Individual blocks are provided in the form of single chips. In order to illustrate the structure and use of bit slices, we will use the AMD 2900* family of chips. Two of the building blocks in this family are a 4-bit ALU chip (AMD 2903) and a microprogram control sequencer chip (AMD 2910). A computer implemented with these chips has a number of 2903s for its data path and uses a 2910 to generate the control store addresses.

The internal structure of the ALU chip is given in Figure 5.11. It consists of a 4-bit ALU, two 4-bit shifters, and a number of 4-bit registers. The ALU provides a full set of arithmetic and logic functions, and the shifters perform shift and rotate operations. The registers consist of 16 general-purpose registers and one register, called the Q register, which can be used for temporary storage of operands. The general-purpose registers are implemented in the form of a two-port memory. This is a random-access memory in which all addressing circuits are duplicated. Hence, two registers can be accessed at the same time, using the two address inputs AA and AB. The contents of these two registers are available at the data outputs A and B, respectively. Data fed to the DATA IN input of the register file is stored in the register pointed to by the AB address. The outputs A and B are fed to the ALU via two multiplexers. Data may also be fed to the inputs of the ALU from sources external to the chip. This allows additional registers to be used when implementing a processor with more than 16 registers. Of course, these inputs can also be used for connecting the ALU chip to the main memory bus.

Several ALU chips may be concatenated to form a wider data path, as illustrated in Figure 5.12. The address inputs to the register file are connected in parallel so that the corresponding registers are selected on all chips. The serial input-output terminals of the shifter are connected to implement a 16-bit shifter. The carry inputs and outputs of the arithmetic and logic units are connected in a similar manner.

The organization of the AMD 2910 microprogram control sequencer is illustrated in Figure 5.13. A control store address is generated at the output of the sequencer from one of four sources. A microprogram counter is used for sequential addresses. At any time, the output of this counter can be pushed onto a stack to allow subroutine calls within the microprogram. Branching is implemented by supplying a branch address to the input of the sequencer chip. A register/loop counter is also provided for storing temporary addresses and for simplifying the implementation of loops in the microprogram.

A simple, 16-bit processor that uses four AMD 2903 chips and one AMD 2910 chip is shown in Figure 5.14. The bit slices are connected to the memory data and address buses via the MDR and MAR registers, respectively. Two MDR registers are used, one for each direction of transfer. The μBA input of the sequencer is connected to the output of a PLA, which provides the starting microprogram address for each machine instruction. It is also connected to one of the fields in the microinstruction register to allow branching in the microprogram.

The above example illustrates how bit slices can be used to implement a processor unit. It is apparent that this approach enables the design of a processor with arbitrary word length, which is also fully microprogrammable. Hence, it can be tailored to meet the requirements of any special task.

* Manufactured by Advanced Micro Devices, Inc., Sunnyvale, California.

Дата добавления: 2015-11-04