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Figure 4-5. Local Bus PCI Target Access

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  7. Figure 2.1. Teaching Process

 


PCI Target Example

A 1 MB prefetchable Local Address Space encompassing Local Bus Addresses 01200000h through 012FFFFFh is to be configured for Local Address Space 0. Assume the BIOS System Resource Manager allocates 1 MB with a PCI Base Address of 34500000h. The Local memory is then accessible at PCI Addresses 34500000h through 345FFFFFh.

a. Program the serial EEPROM as follows:

• Range —FFF00008h [1 MB, decode the upper 12 PCI Address bits, and set the Prefetchable bit (LAS0RR[3]=1)].

• Local Base Address (Remap) —01200001h (Local Base Address for PCI-to-Local accesses). Bit 0 must be set to enable address decoding (LAS0BA[0]=1).

b. PCI Initialization software writes all ones (1) to the PCI Base Address register, then reads it back.

• The PCI 9030 returns a value of FFF00008h, after which the PCI software writes the base address it assigned into the PCI Base Address register(s).

• PCI Base Address —34500008h (PCI Base Address for Access to Local Address Space 0 register, PCIBAR2). The PCI Base Address is always aligned on a boundary determined by address space size. The Prefetchable bit is set (PCIBAR2[3]=1).

 

PCI Target Byte Enables

(Multiplexed Mode)

During a PCI Target transfer, each of five spaces— Spaces 0, 1, 2, and 3, and Expansion ROM—can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP—pins 55, 58-60,

respectively; µBGA—pins M5, P5, M6, N6, respectively) are encoded, based on the configured bus width, as follows.

32-Bit Bus —The four byte enables indicate which of the four bytes are active during a Data cycle:

• LBE3# Byte Enable 3—LAD[31:24]

• LBE2# Byte Enable 2—LAD[23:16]

• LBE1# Byte Enable 1—LAD[15:8]

• LBE0# Byte Enable 0—LAD[7:0]


16-Bit Bus —LBE[3, 1:0]# are encoded to provide BHE#, LAD1, and BLE#, respectively:

• LBE3# Byte High Enable (BHE#)—LAD[15:8]

• LBE2# not used

• LBE1# Address bit 1 (LAD1)

• LBE0# Byte Low Enable (BLE#)—LAD[7:0]

8-Bit Bus —LBE[1:0]# are encoded to provide LAD[1:0], respectively:

• LBE3# not used

• LBE2# not used

• LBE1# Address bit 1 (LAD1)

• LBE0# Address bit 0 (LAD0)

 

During the Address phase, LAD[1:0] are valid address bits with the same value as LBE[1:0]#.

 

PCI Target Byte Enables

(Non-Multiplexed Mode)

During a PCI Target transfer, each of five spaces— Spaces 0, 1, 2, and 3, and Expansion ROM—can be programmed to operate in an 8-, 16-, or 32-bit Local Bus width by encoding the Local Byte Enables (LBE[3:0]#). LBE[3:0]# (PQFP—pins 55, 58-60,

respectively; µBGA—pins M5, P5, M6, N6, respectively) are encoded, based on the configured bus width, as follows.

32-Bit Bus —The four byte enables indicate which of the four bytes are active during a Data cycle:

• LBE3# Byte Enable 3—LD[31:24]

• LBE2# Byte Enable 2—LD[23:16]

• LBE1# Byte Enable 1—LD[15:8]

• LBE0# Byte Enable 0—LD[7:0]

16-Bit Bus —LBE[3, 1:0]# are encoded to provide BHE#, LA1, and BLE#, respectively:

• LBE3# Byte High Enable (BHE#)—LD[15:8]

• LBE2# not used

• LBE1# Address bit 1 (LA1)

• LBE0# Byte Low Enable (BLE#)—LD[7:0]

8-Bit Bus —LBE[1:0]# are encoded to provide LA[1:0], respectively:

• LBE3# not used

• LBE2# not used

• LBE1# Address bit 1 (LA1)

• LBE0# Address bit 0 (LA0)


 

RESPONSE TO FIFO FULL OR EMPTY

Table 4-1 lists the PCI 9030 response to full or empty FIFOs.

 

Дата добавления: 2015-07-10; просмотров: 175 | Нарушение авторских прав

Читайте в этой же книге: Table 2-8. PCI Target Single and Burst Reads | Table 2-9. Byte Number and Lane Cross-Reference | Little Endian | Table 2-14. Lower Byte Lane Transfer— 8-Bit Local Bus | Table 3-2. Serial EEPROM Register Load Sequence | Figure 3-2. PCI 9030 Internal Register Access | Timing Diagram 3-5. PCI Memory Read from Local Configuration Register | Figure 4-1. PCI Target Delayed Read Mode | Figure 4-2. PCI Target Read Ahead Mode | Figure 4-3. PCI Target Write |
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Initialization| Table 4-1. Response to FIFO Full or Empty
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