Figure 4-1. PCI Target Delayed Read Mode

Note: The figure represents a sequence of Bus cycles.

• Write and flush pending Delayed Read (CNTRL[15])

Local Bus Prefetch

Memory-Mapped PCI 9030 Local address spaces can be selectively programmed to enable a Local Bus prefetch (enabled by default in LAS x BRD[5:3]). A Prefetch Counter for each space controls the number

of prefetches to perform in conjunction with each PCI

Read Ahead mode requires that Prefetch be enabled in the LAS x BRD and/or EROMBRD registers for the Memory-Mapped spaces that use Read Ahead mode. The PCI 9030 flushes its Read FIFO for each I/O- Mapped access.

Target read. When the Prefetch Counter is enabled (LAS x BRD[5]=1), the Prefetch Count (LAS x BRD[4:3]) can be set to 0 (disabling prefetch), or to 4, 8 or 16 Lwords (independent of Local Bus width). If the Prefetch Counter is disabled (LAS x BRD[5]=0), the PCI 9030 performs continuous prefetches.

When a PCI Target read is performed and a Local Bus prefetch is enabled for the Local Address space, the PCI 9030 fetches the requested data and continues to read data from sequential addresses (anticipating the PCI Master eventually consuming the additional data). When the PCI 9030 prefetches, if the Prefetch Counter is enabled, the PCI 9030 stops reading from the Local Bus read after reaching the Prefetch Count limit. In Continuous Prefetch mode, if PCI Target Read

PCI Bus

PCI Read request

Read data PCI Bus Master Read

returns with “Sequential Address”

Read data

PCI 9030

Local Bus

  PCI Target Read Ahead mode is set in Internal Registers     Prefetched data is stored in the internal FIFO   PCI 9030 returns prefetched data immediately from internal FIFO without reading again from the Local Bus

PCI 9030 prefetches data from

Local Bus device

PCI 9030 prefetches more data if FIFO space is available

PCI 9030 prefetches more data from Local memory

Ahead mode is disabled (CNTRL[16]=0) (refer to Section 4.2.1.4), the PCI 9030 prefetches as long as space is available in its FIFO, and stops prefetching a few PCI clocks after the PCI Master completes its read. If both Continuous Prefetch and PCI Target Read Ahead modes are enabled, the PCI 9030 continues to prefetch until the Read FIFO is full. If prefetch is disabled (LAS x BRD[5:3]=100), or the address space is mapped as I/O, the PCI 9030 stops after one Read transfer.

Local prefetch must be enabled if PCI Burst reads and Read Ahead mode are utilized.

Refer to Section 2.1.1.4 regarding mapping of PCI 9030 address spaces into an upstream bridge’s Prefetchable Base and Limit registers.

PCI Target Read Ahead Mode

The PCI 9030 also supports PCI Target Read Ahead mode (CNTRL[16]), where prefetched data can be read from the PCI 9030 internal FIFO instead of the Local Bus. The address must be subsequent to the previous address and 32-bit aligned (next address = current address + 4). The PCI Target Read Ahead mode functions can be used with or without PCI Target Delayed Read mode. (Refer to Figure 4-2.)

Дата добавления: 2015-07-10